Messages in this thread | | | Date | Tue, 16 May 2023 12:53:12 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v4 4/6] dt-bindings: Add support for DRAM MRQ GSCs |
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On Tue, May 16, 2023 at 11:12:50AM +0200, Thierry Reding wrote: > I think Peter had to add these explicitly because the defaults are 2 and > 1, respectively, and DTC was warning about this. I suppose the "reg" > property could be adjusted to use the defaults, but on the other hand I > find that it's good if the examples match reality and we need size-cells > to be 2 on Tegra.
Huh, caught out by an abnormal example! If it avoids an error & matches the use-case it seems like a good idea to leave it as-is. Here's an unqualified Reviewed-by: Conor Dooley <conor.dooley@microchip.com> instead of the previous qualified one.
Thanks, Conor. [unhandled content-type:application/pgp-signature] | |