Messages in this thread | ![/](/images/icornerl.gif) | | Date | Fri, 12 May 2023 16:07:00 +0200 | Subject | Re: [PATCH v11 04/11] remoteproc: mediatek: Add MT8195 SCP core 1 operations | From | Matthias Brugger <> |
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On 10/05/2023 08:37, Tinghan Shen wrote: > The SCP rproc driver has a set of chip dependent callbacks for > boot sequence and IRQ handling. Implement these callbacks for MT8195 > SCP core 1. > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> --- > drivers/remoteproc/mtk_common.h | 9 ++++++ > drivers/remoteproc/mtk_scp.c | 56 +++++++++++++++++++++++++++++++++ > 2 files changed, 65 insertions(+) > > diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h > index ea6fa1100a00..c0905aec3b4b 100644 > --- a/drivers/remoteproc/mtk_common.h > +++ b/drivers/remoteproc/mtk_common.h > @@ -47,6 +47,7 @@ > #define MT8192_SCP2SPM_IPC_CLR 0x4094 > #define MT8192_GIPC_IN_SET 0x4098 > #define MT8192_HOST_IPC_INT_BIT BIT(0) > +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) > > #define MT8192_CORE0_SW_RSTN_CLR 0x10000 > #define MT8192_CORE0_SW_RSTN_SET 0x10004 > @@ -56,6 +57,14 @@ > > #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) > > +#define MT8195_CPU1_SRAM_PD 0x1084 > +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 > +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C > +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 > +#define MT8195_CORE1_SW_RSTN_SET 0x20004 > +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 > +#define MT8195_CORE1_WDT_CFG 0x20034 > + > #define SCP_FW_VER_LEN 32 > #define SCP_SHARE_BUFFER_SIZE 288 > > diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c > index e1d93e63d7df..2bf66b1a8d80 100644 > --- a/drivers/remoteproc/mtk_scp.c > +++ b/drivers/remoteproc/mtk_scp.c > @@ -176,6 +176,16 @@ static void mt8192_scp_reset_deassert(struct mtk_scp *scp) > writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); > } > > +static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp) > +{ > + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); > +} > + > +static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp) > +{ > + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); > +} > + > static void mt8183_scp_irq_handler(struct mtk_scp *scp) > { > u32 scp_to_host; > @@ -212,6 +222,18 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) > } > } > > +static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) > +{ > + u32 scp_to_host; > + > + scp_to_host = readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); > + > + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) > + scp_ipi_handler(scp); > + > + writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); > +} > + > static irqreturn_t scp_irq_handler(int irq, void *priv) > { > struct mtk_scp *scp = priv; > @@ -453,6 +475,19 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) > return 0; > } > > +static int mt8195_scp_c1_before_load(struct mtk_scp *scp) > +{ > + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); > + > + /* hold SCP in reset while loading FW. */ > + scp->data->scp_reset_assert(scp); > + > + /* enable MPU for all memory regions */ > + writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); > + > + return 0; > +} > + > static int scp_load(struct rproc *rproc, const struct firmware *fw) > { > struct mtk_scp *scp = rproc->priv; > @@ -625,6 +660,15 @@ static void mt8195_scp_stop(struct mtk_scp *scp) > writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); > } > > +static void mt8195_scp_c1_stop(struct mtk_scp *scp) > +{ > + /* Power off CPU SRAM */ > + scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); > + > + /* Disable SCP watchdog */ > + writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); > +} > + > static int scp_stop(struct rproc *rproc) > { > struct mtk_scp *scp = rproc->priv; > @@ -991,6 +1035,18 @@ static const struct mtk_scp_of_data mt8195_of_data = { > .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT, > }; > > +static const struct mtk_scp_of_data mt8195_of_data_c1 = { > + .scp_clk_get = mt8195_scp_clk_get, > + .scp_before_load = mt8195_scp_c1_before_load, > + .scp_irq_handler = mt8195_scp_c1_irq_handler, > + .scp_reset_assert = mt8195_scp_c1_reset_assert, > + .scp_reset_deassert = mt8195_scp_c1_reset_deassert, > + .scp_stop = mt8195_scp_c1_stop, > + .scp_da_to_va = mt8192_scp_da_to_va, > + .host_to_scp_reg = MT8192_GIPC_IN_SET, > + .host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT, > +}; > + > static const struct of_device_id mtk_scp_of_match[] = { > { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, > { .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data },
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