Messages in this thread | | | Date | Fri, 12 May 2023 14:27:28 +0530 | Subject | Re: [PATCH v7 4/4] pinctrl: qcom: Add SDX75 pincontrol driver | From | Rohit Agarwal <> |
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On 5/11/2023 10:16 PM, Bjorn Andersson wrote: > On Wed, May 10, 2023 at 08:30:25PM +0530, Rohit Agarwal wrote: >> Add initial Qualcomm SDX75 pinctrl driver to support pin configuration >> with pinctrl framework for SDX75 SoC. >> While at it, reordering the SDX65 entry. >> > Nice, some comment below. > >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- > [..] >> diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c >> new file mode 100644 >> index 0000000..6f95c0a >> --- /dev/null >> +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c >> @@ -0,0 +1,1595 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include <linux/module.h> >> +#include <linux/of.h> >> +#include <linux/of_device.h> >> +#include <linux/platform_device.h> >> +#include "pinctrl-msm.h" >> + >> +#define REG_BASE 0x100000 > We typically reference the inner TLMM block and omit this offset... But > I don't have a strong opinion. > > [..] > >> +enum sdx75_functions { >> + msm_mux_gpio, > Please sort these alphabetically. > >> + msm_mux_eth0_mdc, > [..] >> + msm_mux__, >> +}; >> + > [..] >> +static const struct pinfunction sdx75_functions[] = { >> + MSM_PIN_FUNCTION(gpio), >> + MSM_PIN_FUNCTION(eth0_mdc), > Please sort these alphabetically, and please squash individual pins into > their functional group. > > [..] >> + MSM_PIN_FUNCTION(qup_se0_l0), >> + MSM_PIN_FUNCTION(qup_se0_l1), >> + MSM_PIN_FUNCTION(qup_se0_l2), >> + MSM_PIN_FUNCTION(qup_se0_l3), > E.g. this forces the DT writer to write individual -pins for each > signal. Better keep it "qup_se0" and the author is free to group the > pins in their states as they need (and as you know you don't need to > specify all pins for a given function). > > [..] >> +}; >> + >> +/* Every pin is maintained as a single group, and missing or non-existing pin >> + * would be maintained as dummy group to synchronize pin group index with >> + * pin descriptor registered with pinctrl core. >> + * Clients would not be able to request these dummy pin groups. >> + */ > Please omit this comment. > >> +static const struct msm_pingroup sdx75_groups[] = { > [..] >> + [16] = PINGROUP(16, pri_mi2s_ws, qup_se2_l2, qup_se1_l2_mirb, qdss_cti, >> + qdss_cti, _, _, _, _, _), > Please break the rules and leave these lines unwrapped. > >> + [17] = PINGROUP(17, pri_mi2s_data0, qup_se2_l3, qup_se1_l3_mirb, >> + qdss_cti, qdss_cti, _, _, _, _, _), > [..] >> + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _), >> + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _), >> + [133] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x19A000, 16, 0), > Lowercase hex digits please. > >> + [134] = SDC_QDSD_PINGROUP(sdc1_clk, 0x19A000, 14, 6), >> + [135] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x19A000, 11, 3), >> + [136] = SDC_QDSD_PINGROUP(sdc1_data, 0x19A000, 9, 0), >> + [137] = SDC_QDSD_PINGROUP(sdc2_clk, 0x19B000, 14, 6), >> + [138] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x19B000, 11, 3), >> + [139] = SDC_QDSD_PINGROUP(sdc2_data, 0x19B000, 9, 0), >> +}; > [..] >> +static const struct of_device_id sdx75_pinctrl_of_match[] = { >> + { .compatible = "qcom,sdx75-tlmm", .data = &sdx75_pinctrl }, >> + { } >> +}; >> + > [..] >> + >> +MODULE_DESCRIPTION("QTI sdx75 pinctrl driver"); >> +MODULE_LICENSE("GPL"); >> +MODULE_DEVICE_TABLE(of, sdx75_pinctrl_of_match); > Keep the MODULE_DEVICE_TABLE() just below the sdx75_pinctrl_of_match > please, so future readers doesn't need to search for it. Will update all the comments in the next patch version.
Thanks for reviewing, Rohit > Regards, > Bjorn
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