Messages in this thread | | | Date | Wed, 10 May 2023 13:16:23 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v3 04/11] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller |
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Hey Anup,
On Mon, May 08, 2023 at 07:58:35PM +0530, Anup Patel wrote: > + interrupts-extended: > + minItems: 1 > + maxItems: 16384 > + description: > + This property represents the set of CPUs (or HARTs) for which given > + device tree node describes the IMSIC interrupt files. Each node pointed > + to should be a riscv,cpu-intc node, which has a riscv node (i.e. RISC-V > + HART) as parent.
One minor nit here about wording - "riscv node" doesn't seem particularly clear to me, should it be s/riscv node/cpu node/?
My only thing last time around was my misunderstanding, and you also appear to have resolved Rob's complaints, so: Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Just to note, it'd be great if you could CC me on series that I've already reviewed when you resubmit them? Although in this case, if you ran get_maintainer.pl on v6.4-rc1 it'd have told you to CC me anyway ;)
Thanks, Conor. [unhandled content-type:application/pgp-signature] | |