Messages in this thread | | | Date | Wed, 10 May 2023 14:51:07 +0300 (EEST) | From | Ilpo Järvinen <> | Subject | Re: [PATCH v3 4/4] mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers |
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On Thu, 27 Apr 2023, Lee Jones wrote: > On Mon, 17 Apr 2023, Ilpo Järvinen wrote: > > On some MAX 10 cards, the BMC firmware is not available to service > > handshake registers during secure update erase and write phases at > > normal speeds. This problem affects at least hwmon driver. When the MAX > > 10 hwmon driver tries to read the sensor values during a secure update, > > the reads are slowed down (e.g., reading all D5005 sensors takes ~24s > > which is magnitudes worse than the normal <0.02s). > > > > Manage access to the handshake registers using a rw semaphore and a FW > > state variable to prevent accesses during those secure update phases > > and return -EBUSY instead. > > > > If handshake_sys_reg_nranges == 0, don't update bwcfw_state as it is not > > used. This avoids the locking cost. > > > > Co-developed-by: Russ Weight <russell.h.weight@intel.com> > > Signed-off-by: Russ Weight <russell.h.weight@intel.com> > > Co-developed-by: Xu Yilun <yilun.xu@intel.com> > > Signed-off-by: Xu Yilun <yilun.xu@intel.com> > > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > > --- > > drivers/fpga/intel-m10-bmc-sec-update.c | 17 +++++-- > > drivers/mfd/intel-m10-bmc-core.c | 67 ++++++++++++++++++++++++- > > drivers/mfd/intel-m10-bmc-spi.c | 14 ++++++ > > include/linux/mfd/intel-m10-bmc.h | 28 +++++++++++ > > 4 files changed, 121 insertions(+), 5 deletions(-) > > Applied, thanks
Did these end up falling throught the cracks as I've not been able to locate where they were applied?
-- i.
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