Messages in this thread | | | Date | Mon, 03 Apr 2023 14:45:42 +0200 | From | Michael Walle <> | Subject | Re: [PATCH v5 03/10] mtd: spi-nor: core: Update name and description of spansion_set_4byte_addr_mode |
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Am 2023-03-31 09:45, schrieb Tudor Ambarus: > Rename method to spi_nor_set_4byte_addr_mode_brwr and extend its > description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], > BIT(28) and BIT(20). > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > drivers/mtd/spi-nor/core.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 07be81afdc33..e8f6141c0ef6 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -564,15 +564,20 @@ int > spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool > enable) > } > > /** > - * spansion_set_4byte_addr_mode() - Set 4-byte address mode for > Spansion > - * flashes. > + * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using > + * SPINOR_OP_BRWR. Typically used by Spansion flashes. > * @nor: pointer to 'struct spi_nor'. > * @enable: true to enter the 4-byte address mode, false to exit the > 4-byte > * address mode. > * > + * 8-bit volatile bank register used to define A[30:A24] bits. MSB > (bit[7]) is > + * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, > 4-byte > + * address mode is active and A[30:24] bits are don’t care. Write > instruction is > + * SPINOR_OP_BRWR(17h) with 1 byte of data. > + *
No "typically used by spansion"? I guess there is a reason for that.
In any case: Reviewed-by: Michael Walle <michael@walle.cc>
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