Messages in this thread Patch in this message | | | From | Roman Beranek <> | Subject | [PATCH v3 4/7] arm64: dts: allwinner: a64: reset pll-video0 rate | Date | Thu, 27 Apr 2023 11:16:08 +0200 |
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With pll-mipi as its source clock, the exact rate to which TCON0's data clock can be set to is constrained by the current rate of pll-video0. Unless changed on a request of another consumer, the rate of pll-video0 is left as inherited from the bootloader.
The default rate on reset is 297 MHz, a value preferable to what it is later set to in u-boot (294 MHz). This happens unintentionally though, as u-boot, for the sake of simplicity, rounds the rate requested by DE2 driver (297 MHz) to 6 MHz steps.
Reset the PLL to its default rate of 297 MHz.
Signed-off-by: Roman Beranek <me@crly.cz> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index e6a194db420d..cfc60dce80b0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -667,6 +667,9 @@ ccu: clock@1c20000 { clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; + + assigned-clocks = <&ccu CLK_PLL_VIDEO0>; + assigned-clock-rates = <297000000>; }; pio: pinctrl@1c20800 { -- 2.34.1
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