Messages in this thread | | | Date | Thu, 20 Apr 2023 04:02:23 +0300 | Subject | Re: [PATCH v2 13/17] drm/msm/dpu: Factor out shared interrupt register in INTF_BLK macro | From | Dmitry Baryshkov <> |
| |
On 17/04/2023 23:21, Marijn Suijten wrote: > As the INTF block is going to attain more interrupts that don't share > the same MDP_SSPP_TOP0_INTR register, factor out the _reg argument for > the caller to construct the right interrupt index (register and bit > index) to not make the interrupt bit arguments depend on one of multiple > interrupt register indices. This brings us more in line with how PP_BLK > specifies its interrupts and allows for better wrapping in the arrays. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +++++++--- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 16 +++++++--- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 16 +++++++--- > .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 24 +++++++++++---- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 16 +++++++--- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 +++-- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 6 ++-- > .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 6 ++-- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16 +++++++--- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 12 ++++++-- > .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 36 ++++++++++++++++------ > .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 16 +++++++--- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16 +++++++--- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ++-- > 14 files changed, 155 insertions(+), 55 deletions(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-- With best wishes Dmitry
| |