Messages in this thread | | | Date | Mon, 17 Apr 2023 14:57:07 +0300 | From | Dmitry Rokosov <> | Subject | Re: [PATCH v1 1/5] phy: amlogic: during USB PHY clkin obtaining, enable it |
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On Sun, Apr 16, 2023 at 10:54:17PM +0200, Martin Blumenstingl wrote: > Hi Dmitry, > > On Fri, Apr 14, 2023 at 5:24 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote: > [...] > > - priv->clk = devm_clk_get(dev, "xtal"); > > + priv->clk = devm_clk_get_enabled(dev, "xtal"); > Generally this works fine but I wouldn't recommend this approach if: > - there's some required wait time after the clock has been enabled > (see phy_meson_g12a_usb2_init - there's already some required wait > time after triggering the reset) > - clock gating (for power saving) is needed when the dwc3 driver is > unloaded by the PHY driver is not > > In this case: just manually manage the clock in phy_meson_g12a_usb2_{init,exit}
I'm sorry, but I'm not fully understanding your point. Currently, no sleeps are required for this clock and we don't have any logic for power saving (g12a phy_ops doesn't have power_on()/power_off() implementation). However, I believe all of your arguments make sense for the future development of the phy_meson_g12a_usb2 driver. Is that correct?
-- Thank you, Dmitry
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