Messages in this thread | | | Date | Tue, 18 Apr 2023 09:51:02 +0800 | Subject | Re: [PATCH v2 2/3] drivers/perf: add DesignWare PCIe PMU driver | From | Baolin Wang <> |
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On 4/17/2023 9:16 AM, Shuai Xue wrote:
[snip]
>>> + >>> +static void dwc_pcie_pmu_event_update(struct perf_event *event) >>> +{ >>> + u64 counter; >>> + struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu); >>> + struct dwc_pcie_rp_info *rp_info = pmu_to_pcie_info(event->pmu); >>> + struct pci_dev *pdev = rp_info->pdev; >>> + u16 ras_des = rp_info->ras_des; >>> + struct hw_perf_event *hwc = &event->hw; >>> + enum dwc_pcie_event_type type = DWC_PCIE_EVENT_TYPE(event); >>> + u64 delta, prev, now; >>> + >>> + do { >>> + prev = local64_read(&hwc->prev_count); >>> + >>> + if (type == DWC_PCIE_LANE_EVENT) >>> + dwc_pcie_pmu_read_event_counter(pdev, ras_des, &counter); >>> + else if (type == DWC_PCIE_TIME_BASE_EVENT) >>> + dwc_pcie_pmu_read_base_time_counter(pdev, ras_des, >>> + &counter); >>> + else >>> + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); >>> + >>> + now = counter; >>> + } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); >>> + >>> + delta = now - prev; >> >> This can be overflow? better to add a mask to avoid possible overflow. > > I think it can not. This Root Complex supports up to PCIe Gen5 (32 GT/s) > and one root port support up to x16 lanes, with peek bandwidth 64 GB/s. > On Yitian 710, one root port is x4 lane with peak bandwidth 16 GB/s. > The counter is 64 bit width with 16 bytes unit. > > 2^64*16/(64*10^9)/60/60/24/365 = 146 years > > For x16 root port, it will not overflow within 146 yeasr and for yitian 710, > it will never overflow in my life too.
However the lane event counter is 32bit, so still a maximum counter mask is preferable.
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