Messages in this thread | | | Date | Mon, 17 Apr 2023 17:56:55 +0100 | From | Jonathan Cameron <> | Subject | Re: [PATCH v3 4/6] cxl/pci: Add RCH downstream port error logging |
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> > >> + > >> + writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); > >> + writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); > >> + > >> + return true; > >> +} > > = > >> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c > >> index bde1fffab09e..dfa6fcfc428a 100644 > >> --- a/drivers/cxl/core/regs.c > >> +++ b/drivers/cxl/core/regs.c > >> @@ -198,6 +198,7 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, > >> > >> return ret_val; > >> } > >> +EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, CXL); > >> > >> int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, > >> struct cxl_register_map *map, unsigned long map_mask) > >> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > >> index df64c402e6e6..dae3f141ffcb 100644 > >> --- a/drivers/cxl/cxl.h > >> +++ b/drivers/cxl/cxl.h > >> @@ -66,6 +66,8 @@ > >> #define CXL_DECODER_MIN_GRANULARITY 256 > >> #define CXL_DECODER_MAX_ENCODED_IG 6 > >> > >> +#define PCI_AER_CAPABILITY_LENGTH 56 > > > > Odd place to find a PCI specific define. Also a spec reference is > > always good for these. What's the the length of? PCI r6.0 has > > cap going up to address 0x5c so length 0x60. This seems to be igoring > > the header log register. > > > > This was to avoid including the TLP log at 0x38+. > > I can use sizeof(struct aer_capability_regs) or sizeof(*aer_regs) instead. > It's the same 38h(56) and will allow me to remove this #define in the > patchset revision.
That works better than a define that people might think is more generic. Otherwise you get PCI_AER_CAP_WITHOUT_TLP_LOG_LENGTH or something equally horrible. (or define the TLP_LOG length as another define and subtract that?)
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