Messages in this thread | | | From | "Lad, Prabhakar" <> | Date | Thu, 13 Apr 2023 22:06:06 +0100 | Subject | Re: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP RISC-V core |
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On Thu, Apr 13, 2023 at 7:46 PM Conor Dooley <conor@kernel.org> wrote: > > > Is > > dma-noncoherent.c also valid for RISCV-32? If not then we can make > > pmem.c compile conditionally if DMA non-coherenet is enabled and we > > make DMA non-coherent depend on 64bit. > > Could you drop the {s,l}d in exchange for {s,l}w instead, or am I > progressing even further into braino territory? Just the direct exchange wont work in addition shifting + oring to take care of 64-bit will require. (Correct me if I'm wrong here)
I was wondering now if we need to store/restore the s0 and ra registers. I stumbled on an X86 implementation which has call [0] in the ALTERNATIVE_X() macro but here we dont store/restore the registers. Is the RISC-V implementation of ALT macro different compared to x86?
[0] https://elixir.bootlin.com/linux/latest/source/arch/x86/include/asm/uaccess_64.h#L105
Cheers, Prabhakar
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