Messages in this thread | | | Date | Wed, 12 Apr 2023 14:09:33 +0200 | Subject | Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle | From | Konrad Dybcio <> |
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On 12.04.2023 13:55, Krzysztof Kozlowski wrote: > On 12/04/2023 13:47, Konrad Dybcio wrote: >>> For unrelated reasons I actually have some patches for this, that switch >>> the /smd top-level node to a "remoteproc-like" node dedicated to the >>> RPM, similar to how WCNSS/ADSP/Modem/etc are represented. I need this to >>> add additional (optional) properties like "resets" and "iommus" for the >>> RPM, but it would allow adding arbitrary subnodes as well: >>> >>> https://github.com/msm8916-mainline/linux/commit/35231ac28703805daa8220f1233847c7df34589e >>> >>> I could finish those up and post them if that would help... >> Krzysztof, what do you think? > > I don't know what is there in MSM8916 and how it should be represented. Similarly to other Qualcomm SoCs, MSM8916 has a RPM (Cortex-M3) core, which communicates over the SMD protocol (or G-LINK on >=8996).
The Qualcomm firmware loads the RPM fw blob and sets it up early in the boot process, but msm8916-mainline folks managed to get TF-A going and due to it being less.. invasive.. than the Qualcomm TZ, RPM needs a bit more handling to be accessible.
The M3 core is wired up through the CNoC bus and we communicate with it through the MSG RAM and the "APCS mailbox".
Konrad > > Best regards, > Krzysztof >
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