Messages in this thread | | | Date | Wed, 12 Apr 2023 16:14:21 -0700 | Subject | Re: [net-next Patch v7 5/6] octeontx2-pf: Add support for HTB offload | From | Jacob Keller <> |
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On 4/10/2023 12:29 AM, Hariprasad Kelam wrote: > +static void __otx2_qos_txschq_cfg(struct otx2_nic *pfvf, > + struct otx2_qos_node *node, > + struct nix_txschq_config *cfg) > +{ > + struct otx2_hw *hw = &pfvf->hw; > + int num_regs = 0; > + u64 maxrate; > + u8 level; > + > + level = node->level; > + > + /* program txschq registers */ > + if (level == NIX_TXSCH_LVL_SMQ) { > + cfg->reg[num_regs] = NIX_AF_SMQX_CFG(node->schq); > + cfg->regval[num_regs] = ((u64)pfvf->tx_max_pktlen << 8) | > + OTX2_MIN_MTU; > + cfg->regval[num_regs] |= (0x20ULL << 51) | (0x80ULL << 39) | > + (0x2ULL << 36); > + num_regs++; > + > + /* configure parent txschq */ > + cfg->reg[num_regs] = NIX_AF_MDQX_PARENT(node->schq); > + cfg->regval[num_regs] = node->parent->schq << 16; > + num_regs++; > + > + /* configure prio/quantum */ > + if (node->qid == OTX2_QOS_QID_NONE) { > + cfg->reg[num_regs] = NIX_AF_MDQX_SCHEDULE(node->schq); > + cfg->regval[num_regs] = node->prio << 24 | > + mtu_to_dwrr_weight(pfvf, > + pfvf->tx_max_pktlen); > + num_regs++; > + goto txschq_cfg_out; > + } > + > + /* configure prio */ > + cfg->reg[num_regs] = NIX_AF_MDQX_SCHEDULE(node->schq); > + cfg->regval[num_regs] = (node->schq - > + node->parent->prio_anchor) << 24; > + num_regs++; > + > + /* configure PIR */ > + maxrate = (node->rate > node->ceil) ? node->rate : node->ceil; > + > + cfg->reg[num_regs] = NIX_AF_MDQX_PIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, maxrate, 65536); > + num_regs++; > + > + /* configure CIR */ > + if (!test_bit(QOS_CIR_PIR_SUPPORT, &pfvf->hw.cap_flag)) { > + /* Don't configure CIR when both CIR+PIR not supported > + * On 96xx, CIR + PIR + RED_ALGO=STALL causes deadlock > + */ > + goto txschq_cfg_out; > + } > + > + cfg->reg[num_regs] = NIX_AF_MDQX_CIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, node->rate, 65536); > + num_regs++; > + } else if (level == NIX_TXSCH_LVL_TL4) { > + /* configure parent txschq */ > + cfg->reg[num_regs] = NIX_AF_TL4X_PARENT(node->schq); > + cfg->regval[num_regs] = node->parent->schq << 16; > + num_regs++; > + > + /* return if not htb node */ > + if (node->qid == OTX2_QOS_QID_NONE) { > + cfg->reg[num_regs] = NIX_AF_TL4X_SCHEDULE(node->schq); > + cfg->regval[num_regs] = node->prio << 24 | > + mtu_to_dwrr_weight(pfvf, > + pfvf->tx_max_pktlen); > + num_regs++; > + goto txschq_cfg_out; > + } > + > + /* configure priority */ > + cfg->reg[num_regs] = NIX_AF_TL4X_SCHEDULE(node->schq); > + cfg->regval[num_regs] = (node->schq - > + node->parent->prio_anchor) << 24; > + num_regs++; > + > + /* configure PIR */ > + maxrate = (node->rate > node->ceil) ? node->rate : node->ceil; > + cfg->reg[num_regs] = NIX_AF_TL4X_PIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, maxrate, 65536); > + num_regs++; > + > + /* configure CIR */ > + if (!test_bit(QOS_CIR_PIR_SUPPORT, &pfvf->hw.cap_flag)) { > + /* Don't configure CIR when both CIR+PIR not supported > + * On 96xx, CIR + PIR + RED_ALGO=STALL causes deadlock > + */ > + goto txschq_cfg_out; > + } > + > + cfg->reg[num_regs] = NIX_AF_TL4X_CIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, node->rate, 65536); > + num_regs++; > + } else if (level == NIX_TXSCH_LVL_TL3) { > + /* configure parent txschq */ > + cfg->reg[num_regs] = NIX_AF_TL3X_PARENT(node->schq); > + cfg->regval[num_regs] = node->parent->schq << 16; > + num_regs++; > + > + /* configure link cfg */ > + if (level == pfvf->qos.link_cfg_lvl) { > + cfg->reg[num_regs] = NIX_AF_TL3_TL2X_LINKX_CFG(node->schq, hw->tx_link); > + cfg->regval[num_regs] = BIT_ULL(13) | BIT_ULL(12); > + num_regs++; > + } > + > + /* return if not htb node */ > + if (node->qid == OTX2_QOS_QID_NONE) { > + cfg->reg[num_regs] = NIX_AF_TL3X_SCHEDULE(node->schq); > + cfg->regval[num_regs] = node->prio << 24 | > + mtu_to_dwrr_weight(pfvf, > + pfvf->tx_max_pktlen); > + num_regs++; > + goto txschq_cfg_out; > + } > + > + /* configure priority */ > + cfg->reg[num_regs] = NIX_AF_TL3X_SCHEDULE(node->schq); > + cfg->regval[num_regs] = (node->schq - > + node->parent->prio_anchor) << 24; > + num_regs++; > + > + /* configure PIR */ > + maxrate = (node->rate > node->ceil) ? node->rate : node->ceil; > + cfg->reg[num_regs] = NIX_AF_TL3X_PIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, maxrate, 65536); > + num_regs++; > + > + /* configure CIR */ > + if (!test_bit(QOS_CIR_PIR_SUPPORT, &pfvf->hw.cap_flag)) { > + /* Don't configure CIR when both CIR+PIR not supported > + * On 96xx, CIR + PIR + RED_ALGO=STALL causes deadlock > + */ > + goto txschq_cfg_out; > + } > + > + cfg->reg[num_regs] = NIX_AF_TL3X_CIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, node->rate, 65536); > + num_regs++; > + } else if (level == NIX_TXSCH_LVL_TL2) { > + /* configure parent txschq */ > + cfg->reg[num_regs] = NIX_AF_TL2X_PARENT(node->schq); > + cfg->regval[num_regs] = hw->tx_link << 16; > + num_regs++; > + > + /* configure link cfg */ > + if (level == pfvf->qos.link_cfg_lvl) { > + cfg->reg[num_regs] = NIX_AF_TL3_TL2X_LINKX_CFG(node->schq, hw->tx_link); > + cfg->regval[num_regs] = BIT_ULL(13) | BIT_ULL(12); > + num_regs++; > + } > + > + /* return if not htb node */ > + if (node->qid == OTX2_QOS_QID_NONE) { > + cfg->reg[num_regs] = NIX_AF_TL2X_SCHEDULE(node->schq); > + cfg->regval[num_regs] = node->prio << 24 | > + mtu_to_dwrr_weight(pfvf, > + pfvf->tx_max_pktlen); > + num_regs++; > + goto txschq_cfg_out; > + } > + > + /* check if node is root */ > + if (node->qid == OTX2_QOS_QID_INNER && !node->parent) { > + cfg->reg[num_regs] = NIX_AF_TL2X_SCHEDULE(node->schq); > + cfg->regval[num_regs] = TXSCH_TL1_DFLT_RR_PRIO << 24 | > + mtu_to_dwrr_weight(pfvf, > + pfvf->tx_max_pktlen); > + num_regs++; > + goto txschq_cfg_out; > + } > + > + /* configure priority/quantum */ > + cfg->reg[num_regs] = NIX_AF_TL2X_SCHEDULE(node->schq); > + cfg->regval[num_regs] = (node->schq - > + node->parent->prio_anchor) << 24; > + num_regs++; > + > + /* configure PIR */ > + maxrate = (node->rate > node->ceil) ? node->rate : node->ceil; > + cfg->reg[num_regs] = NIX_AF_TL2X_PIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, maxrate, 65536); > + num_regs++; > + > + /* configure CIR */ > + if (!test_bit(QOS_CIR_PIR_SUPPORT, &pfvf->hw.cap_flag)) { > + /* Don't configure CIR when both CIR+PIR not supported > + * On 96xx, CIR + PIR + RED_ALGO=STALL causes deadlock > + */ > + goto txschq_cfg_out; > + } > + > + cfg->reg[num_regs] = NIX_AF_TL2X_CIR(node->schq); > + cfg->regval[num_regs] = > + otx2_get_txschq_rate_regval(pfvf, node->rate, 65536); > + num_regs++; > + } > + > +txschq_cfg_out: > + cfg->num_regs = num_regs; > +} > +
That is a lot of code for one function.. Any chance it could be split into some helpers?
This patch itself is also much larger than I was expecting. I guess most of it is in the new file implementing the new HTB offload, but its hard to digest in a single patch.
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