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SubjectRe: [PATCH v1 1/3] dt-binding: pci: add JH7110 PCIe dt-binding documents.
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On 10/04/2023 11:05, Minda Chen wrote:
>>> +
>>> + starfive,stg-syscon:
>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>> + items:
>>> + items:
>>> + - description: phandle to System Register Controller stg_syscon node.
>>> + - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + description:
>>> + The phandle to System Register Controller syscon node and the offset
>>> + of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset
>>> + for PCIe.
>>> +
>>> + pwren-gpios:
>>> + description: Should specify the GPIO for controlling the PCI bus device power on.
>>
>> What are these? Different than defined in gpio-consumer-common?
>>
> power gpio board level configuration. It it not a requried property

What is "board level configuration"? Again - is it different than
powerdown-gpios from gpio-consumer-common.yaml?



Best regards,
Krzysztof

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