Messages in this thread | | | Date | Tue, 07 Mar 2023 13:48:20 -0800 (PST) | Subject | Re: [PATCH v2 3/4] riscv: dts: starfive: Add crypto and DMA node for VisionFive 2 | From | Palmer Dabbelt <> |
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On Mon, 30 Jan 2023 07:42:41 PST (-0800), jiajie.ho@starfivetech.com wrote: > Add StarFive cryptographic module and dedicated DMA controller node to > VisionFive 2 SoCs. > > Co-developed-by: Huan Feng <huan.feng@starfivetech.com> > Signed-off-by: Huan Feng <huan.feng@starfivetech.com> > Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 27 ++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 4ac159d79d66..bb134a8a89c9 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -455,5 +455,32 @@ uart5: serial@12020000 { > reg-shift = <2>; > status = "disabled"; > }; > + > + sdma: dma@16008000 { > + compatible = "arm,pl080", "arm,primecell"; > + arm,primecell-periphid = <0x00041080>; > + reg = <0x0 0x16008000 0x0 0x4000>; > + interrupts = <29>; > + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, > + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; > + clock-names = "hclk", "apb_pclk"; > + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; > + lli-bus-interface-ahb1; > + mem-bus-interface-ahb1; > + memcpy-burst-size = <256>; > + memcpy-bus-width = <32>; > + #dma-cells = <2>; > + }; > + > + crypto: crypto@16000000 { > + compatible = "starfive,jh7110-crypto"; > + reg = <0x0 0x16000000 0x0 0x4000>; > + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, > + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; > + clock-names = "hclk", "ahb"; > + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; > + dmas = <&sdma 1 2>, <&sdma 0 2>; > + dma-names = "tx", "rx"; > + }; > }; > };
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
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