Messages in this thread | | | From | Peter Newman <> | Date | Mon, 6 Mar 2023 14:14:33 +0100 | Subject | Re: [PATCH v2 09/18] x86/resctrl: Allow resctrl_arch_rmid_read() to sleep |
| |
Hi James,
On Mon, Mar 6, 2023 at 12:34 PM James Morse <james.morse@arm.com> wrote: > On 23/01/2023 15:33, Peter Newman wrote: > > On Fri, Jan 13, 2023 at 6:56 PM James Morse <james.morse@arm.com> wrote: > >> MPAM's cache occupancy counters can take a little while to settle once > >> the monitor has been configured. The maximum settling time is described > >> to the driver via a firmware table. The value could be large enough > >> that it makes sense to sleep. > > > > Would it be easier to return an error when reading the occupancy count > > too soon after configuration? On Intel it is already normal for counter > > reads to fail on newly-allocated RMIDs. > > For x86, you have as many counters as there are RMIDs, so there is no issue just accessing > the counter.
I should have said AMD instead of Intel, because their implementations have far fewer counters than RMIDs.
> > With MPAM there may be as few as 1 monitor for the CSU (cache storage utilisation) > counter, which needs to be multiplexed between different PARTID to find the cache > occupancy (This works for CSU because its a stable count, it doesn't work for the > bandwidth monitors) > On such a platform the monitor needs to be allocated and programmed before it reads a > value for a particular PARTID/CLOSID. If you had two threads trying to read the same > counter, they could interleave perfectly to prevent either thread managing to read a value. > The 'not ready' time is advertised in a firmware table, and the driver will wait at most > that long before giving up and returning an error.
Likewise, on AMD, a repeating sequence of tasks which are LRU in terms of counter -> RMID allocation could prevent RMID event reads from ever returning a value.
The main difference I see with MPAM is that software allocates the counters instead of hardware, but the overall behavior sounds the same.
The part I object to is introducing the wait to the counter read because existing software already expects an immediate error when reading a counter too soon. To produce accurate data, these readings are usually read at intervals of multiple seconds.
Instead, when configuring a counter, could you use the firmware table value to compute the time when the counter will next be valid and return errors on read requests received before that?
-Peter
| |