Messages in this thread | | | Date | Fri, 31 Mar 2023 14:55:38 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v4 09/12] x86/mtrr: construct a memory map with cache modes |
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On Wed, Mar 29, 2023 at 03:39:35PM +0200, Juergen Gross wrote: > No. :-)
Because?
> The final form of the code is the result of an iterative process. :-)
I have a similar iterative process: until it hasn't been reviewed and explained properly, this is not going anywhere.
So however you wanna do it, fine by me.
> I've reused the wording from cleanup.c (just above amd_special_default_mtrr()).
That got added with K8. K8 is ancient history so nothing magic about that anymore. It is basically a bit in the SYSCFG MSR which says that
[4G ... TOP_MEM2]
is WB.
> > Why not in mtrr_bp_init()? That is the first CPU. > > Yeah, but generic_set_mtrr() can be called after boot, too.
That function sets a single MTRR register so you'd have to merge the ranges, AFAICT. Not rebuild the whole map...
> Umm, not really. I want to do the copy even in the Xen PV case.
How about some comments? Or you're expecting me to be able to read your mind?!
;-\
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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