Messages in this thread | | | Date | Fri, 31 Mar 2023 13:45:27 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v7 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core |
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On Thu, Mar 30, 2023 at 09:42:16PM +0100, Prabhakar wrote:
> +STANDALONE CACHE CONTROLLER DRIVERS
> +F: include/cache
This can go since the file no longer exists.
> +config AX45MP_L2_CACHE > + bool "Andes Technology AX45MP L2 Cache controller" > + depends on RISCV && RISCV_DMA_NONCOHERENT
This can just be depends on RISCV_DMA_NONCOHERENT, since that's only defined on RISC-V.
> +static void ax45mp_get_l2_line_size(struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.of_node; > + struct device *dev = &pdev->dev; > + int ret; > + > + ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv->ax45mp_cache_line_size); > + if (ret) { > + dev_err(dev, "Failed to get cache-line-size, defaulting to 64 bytes\n"); > + ax45mp_priv->ax45mp_cache_line_size = AX45MP_CACHE_LINE_SIZE; > + } > + > + if (ax45mp_priv->ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) { > + dev_err(dev, "Expected cache-line-size to be 64 bytes (found:%u). Defaulting to 64 bytes\n", > + ax45mp_priv->ax45mp_cache_line_size); > + ax45mp_priv->ax45mp_cache_line_size = AX45MP_CACHE_LINE_SIZE; > + }
I forget, why are we doing this defaulting rather than falling over immediately if we detect the property is missing or wrong?
> +}
> +static const struct riscv_cache_ops ax45mp_cmo_ops = { > + .clean_range = &ax45mp_cpu_dma_wb_range, > + .inv_range = &ax45mp_cpu_dma_inval_range, > + .flush_range = &ax45mp_cpu_dma_flush_range, > +};
I think it would be nice if your driver functions matched the names used by the ops. (and as I said on the other patch, I think the ops should match the cross-arch naming.
Otherwise, looks grand - although I think I was mostly happy with the last revision too.a
Cheers, Conor. [unhandled content-type:application/pgp-signature] | |