Messages in this thread | | | From | Fabio Estevam <> | Date | Fri, 31 Mar 2023 07:29:14 -0300 | Subject | Re: [PATCH] clk: imx: imx6sx: spdif clock rate is too high for asrc |
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On Fri, Mar 31, 2023 at 4:15 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote: > > From: Shengjiu Wang <shengjiu.wang@nxp.com> > > spdif clock is one of the asrc clock source, which is used > for ideal ratio mode. when set to 98.304MHz, it cause the > divider of asrc input clock and output clock exceed the > maximum value, and asrc driver saturate the value to maximum > value, which will cause the ASRC's performance very bad. > So we need to set spdif clock to a proper rate. which make asrc > divider not exceed maximum value, at least one of divider not > exceed maximum value. > The target is spdif clock rate / output(or input) sample rate > less than 1024(which is maximum divider).
Please add a Fixes tag.
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