Messages in this thread Patch in this message | | | Date | Fri, 31 Mar 2023 15:55:20 +1000 | Subject | Re: [PATCH V3 7/7] arm64: dts: imx8mp: add interconnect for hsio blk ctrl | From | Greg Ungerer <> |
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Hi Marco,
On 29/3/23 01:11, Marco Felsch wrote: > Hi Greg, > > On 23-03-29, Greg Ungerer wrote: >> Hi Marco, > > ... > >>> I forgot to ask: Does your i.MX8MP have a VPU? There are i.MX8MP devices >>> (don't know the name) which don't have support for certain IPs. If this >> >> The hardware platform I have is using the MIMX8ML4CVNKZAB "i.MX 8M Plus QuadLite" >> (https://www.nxp.com/part/MIMX8ML4CVNKZAB#/) which does not have the hardware >> video encode/decoder module (like the "i.MX 8M Plus Quad" parts). > > and that's the problem :) You need to update your bootloader to a > version which support disabling the VPU nodes else you will always see > the errors.
I agree this is the problem, I don't agree that the boot loader is the only place to fix this :-) I should be able to generate a working devicetree blob from the kernel that is good, and ready to use no runtime changes required I figure.
It is not overly difficult to break out the vpu nodes and have them only included when you have a board that has the iMX8MP-quad with the VPU hardware blocks.
Example patch attached.
Regards GregFrom c2e6af08d090216aae8c9f992a9e64014147be9f Mon Sep 17 00:00:00 2001 From: Greg Ungerer <gerg@linux-m68k.org> Date: Fri, 31 Mar 2023 15:47:55 +1000 Subject: [PATCH] arm64: dts: imx8mp: separate out VPU nodes
The VPU hardware module is not included in all variants of the imx8mp SoC. It will cause errors trying to initialize when not present:
imx-pgc imx-pgc-domain.8: failed to command PGC
Break out the VPU nodes into a new dtsi file so that only platforms that need them include them. Platforms with the "lite" version of the imx8mp don't need to include it.
Signed-off-by: Greg Ungerer <gerg@kernel.org> --- .../boot/dts/freescale/imx8mp-beacon-kit.dts | 1 + .../dts/freescale/imx8mp-debix-model-a.dts | 1 + .../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 + .../freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 1 + .../boot/dts/freescale/imx8mp-msc-sm2s.dtsi | 1 + .../dts/freescale/imx8mp-phycore-som.dtsi | 1 + .../boot/dts/freescale/imx8mp-tqma8mpql.dtsi | 1 + .../dts/freescale/imx8mp-venice-gw74xx.dts | 1 + .../boot/dts/freescale/imx8mp-verdin.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mp-vpu.dtsi | 80 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 77 ------------------ 12 files changed, 90 insertions(+), 77 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-vpu.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index cdae45a48c2c..a8dde370476f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -8,6 +8,7 @@ #include <dt-bindings/usb/pd.h> #include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" #include "imx8mp-beacon-som.dtsi" / { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index 2876d18f2a38..19b780594957 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -11,6 +11,7 @@ #include <dt-bindings/usb/pd.h> #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" / { model = "Polyhex Debix Model A i.MX8MPlus board"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 9cdd4234c4ca..7383222f628a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -4,6 +4,7 @@ */ #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" / { model = "DH electronics i.MX8M Plus DHCOM SoM"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7816853162b3..5a146e7fa9d2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -7,6 +7,7 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" / { model = "NXP i.MX8MPlus EVK board"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts index a02b31c42db4..d7a621938720 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" #include "imx8mp-icore-mx8mp.dtsi" #include <dt-bindings/usb/pd.h> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi index 5dbec71747c3..1d3bb17ac92a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" #include <dt-bindings/net/ti-dp83867.h> / { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index ecc4bce6db97..12ed5402a4b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/net/ti-dp83867.h> #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" / { model = "PHYTEC phyCORE-i.MX8MP"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi index ebc29a950ba9..e3db32505d0b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi @@ -5,6 +5,7 @@ */ #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" / { model = "TQ-Systems i.MX8MPlus TQMa8MPxL"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index eb51d648359b..c4552da30789 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -11,6 +11,7 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" / { model = "Gateworks Venice GW74xx i.MX8MP board"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 0dd6180a8e39..100b3ea2bd4d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> #include <dt-bindings/pwm/pwm.h> #include "imx8mp.dtsi" +#include "imx8mp-vpu.dtsi" / { chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-vpu.dtsi new file mode 100644 index 000000000000..3ca1bdf6262c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-vpu.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +&gpc { + pgc { + pgc_vpumix: power-domain@19 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; + clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + }; + + pgc_vpu_g1: power-domain@20 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + pgc_vpu_g2: power-domain@21 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; + + pgc_vpu_vc8000e: power-domain@22 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + }; + }; +}; + +&soc { + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; + }; + + vpumix_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + #power-domain-cells = <1>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; + power-domain-names = "bus", "g1", "g2", "vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, + <&clk IMX8MP_CLK_VPU_G2_ROOT>, + <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + clock-names = "g1", "g2", "vc8000e"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, <600000000>; + interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; + interconnect-names = "g1", "g2", "vc8000e"; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 2dd60e3252f3..e35409db3240 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -625,41 +625,6 @@ pgc_ispdwp: power-domain@18 { reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; }; - - pgc_vpumix: power-domain@19 { - #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; - clocks =<&clk IMX8MP_CLK_VPU_ROOT>; - }; - - pgc_vpu_g1: power-domain@20 { - #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; - }; - - pgc_vpu_g2: power-domain@21 { - #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; - clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; - }; - - pgc_vpu_vc8000e: power-domain@22 { - #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; - clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; - }; - - pgc_mlmix: power-domain@24 { - #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_MLMIX>; - clocks = <&clk IMX8MP_CLK_ML_AXI>, - <&clk IMX8MP_CLK_ML_AHB>, - <&clk IMX8MP_CLK_NPU_ROOT>; - }; }; }; }; @@ -1340,48 +1305,6 @@ gpu2d: gpu@38008000 { power-domains = <&pgc_gpu2d>; }; - vpu_g1: video-codec@38300000 { - compatible = "nxp,imx8mm-vpu-g1"; - reg = <0x38300000 0x10000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; - assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; - assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; - assigned-clock-rates = <600000000>; - power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; - }; - - vpu_g2: video-codec@38310000 { - compatible = "nxp,imx8mq-vpu-g2"; - reg = <0x38310000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; - assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <500000000>; - power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; - }; - - vpumix_blk_ctrl: blk-ctrl@38330000 { - compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; - reg = <0x38330000 0x100>; - #power-domain-cells = <1>; - power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, - <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; - power-domain-names = "bus", "g1", "g2", "vc8000e"; - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, - <&clk IMX8MP_CLK_VPU_G2_ROOT>, - <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; - clock-names = "g1", "g2", "vc8000e"; - assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; - assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; - assigned-clock-rates = <600000000>, <600000000>; - interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, - <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, - <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; - interconnect-names = "g1", "g2", "vc8000e"; - }; - gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, -- 2.25.1
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