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Tue, 28 Mar 2023 13:43:54 +0000 (UTC) From: Mark Brown To: Tharunkumar Pasumarthi - I67821 CC: "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH SPI for-next] spi: microchip: pci1xxxx: Fix minor bugs in spi-pci1xxxx driver Thread-Topic: [PATCH SPI for-next] spi: microchip: pci1xxxx: Fix minor bugs in spi-pci1xxxx driver Thread-Index: AQHZYXtoAkmg0Jz2n0m0Uw2JIelspg== X-MS-Exchange-MessageSentRepresentingType: 1 Date: Tue, 28 Mar 2023 13:43:50 +0000 Message-ID: <97c57e1b-9779-4e36-9eac-754fdcb9c504@sirena.org.uk> References: <20230328054212.139312-1-tharunkumar.pasumarthi@microchip.com> In-Reply-To: <20230328054212.139312-1-tharunkumar.pasumarthi@microchip.com> X-MS-Exchange-Organization-AuthAs: Anonymous X-MS-Exchange-Organization-AuthSource: DM6NAM10FT084.eop-nam10.prod.protection.outlook.com X-MS-Has-Attach: yes X-MS-Exchange-Organization-Network-Message-Id: 691ea8b3-38a8-46ef-d8b5-08db2f928928 X-MS-TNEF-Correlator: x-ms-publictraffictype: Email received-spf: None (esa1.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@dfw.source.kernel.org) identity=helo; client-ip=139.178.84.217; receiver=esa1.microchip.iphmx.com; envelope-from="broonie@kernel.org"; x-sender="postmaster@dfw.source.kernel.org"; x-conformance=spf_only Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="2PS2/CgMOCO2Hp2O" MIME-Version: 1.0 --2PS2/CgMOCO2Hp2O Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Mar 28, 2023 at 11:12:12AM +0530, Tharun Kumar P wrote: > Following bugs are fixed in this patch: > 1. pci1xxxx_spi_resume API masks SPI interrupt bit which prohibits > firing of interrupt to the host at the end of the transaction after > suspend-resume. This patch unmasks this bit at resume. > 2. In=A0pci1xxxx_spi_transfer_one API, length of SPI transaction gets > cleared by unmasking length field. Set length of transaction after > unmasking length field. > 3. Remove support for disabling chip select as hardware does not support > the same. As covered in submitting-patches.rst you should send one patch per change, this makes things much easier to review. > drivers/spi/spi-pci1xxxx.c | 12 ++++-------- > 1 file changed, 4 insertions(+), 8 deletions(-) The subject says this is a patch for the microchip driver... > /* Set the DEV_SEL bits of the SPI_MST_CTL_REG */ > regval =3D readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); > - if (enable) { > + if (!enable) { > regval &=3D ~SPI_MST_CTL_DEVSEL_MASK; > regval |=3D (spi_get_chipselect(spi, 0) << 25); > writel(regval, > par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); > - } else { > - regval &=3D ~(spi_get_chipselect(spi, 0) << 25); > - writel(regval, > - par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); > - I am unclear how chip select will ever be asserted with this change? Now the value is only written if we are disabling. --2PS2/CgMOCO2Hp2O Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmQi7xIACgkQJNaLcl1U h9Ch8gf+O/MluZL0YuDTHhZLLMwc6B5ISaKg7aLC6AxuIXjQ/I04oR+OhSexo/p7 KvgYa4WouYJxeZim7h98p2qWUjMrTTfUltXnbifLd6L1N3g/l/S1jr6DPGaa2SwV KiFB5DO7cNuc6GVun1Sv2Q/15w39UbMwRUfqioeHluDn2Na1dCjab8t8G2AokU0B gzWGZ7mSU+aSf+kmNlDHImh6rsQJqDIkD39CxLppbcyTSIB3WBI2kyCY5LbUhxUE wdGKDtuVwyfHZHBY/EY+ejyb0mccWoxdshAlcyCN6gj5WVo8Y45B5eoZliBEc60b 6epymPQxByl5AL6IX+XyDTxHg12TLA== =eYBI -----END PGP SIGNATURE----- --2PS2/CgMOCO2Hp2O-- --_002_754b57849925e48401e6ebb3d206c966a8a08800camelmicrochipc_--