Messages in this thread | | | Date | Fri, 24 Mar 2023 12:41:05 -0500 | Subject | Re: [PATCH v2 5/5] cxl/pci: Add RCH downstream port error logging | From | Terry Bowman <> |
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I added a comment below.
On 3/24/23 01:30, kernel test robot wrote: > Hi Terry, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on pci/next] > [also build test ERROR on pci/for-linus efi/next cxl/next linus/master v6.3-rc3 next-20230323] > [cannot apply to cxl/pending] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Terry-Bowman/cxl-pci-Add-RCH-downstream-port-AER-and-RAS-register-discovery/20230324-054044 > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next > patch link: https://lore.kernel.org/r/20230323213808.398039-6-terry.bowman%40amd.com > patch subject: [PATCH v2 5/5] cxl/pci: Add RCH downstream port error logging > config: i386-randconfig-a001 (https://download.01.org/0day-ci/archive/20230324/202303241458.BV292BDH-lkp@intel.com/config) > compiler: gcc-11 (Debian 11.3.0-8) 11.3.0 > reproduce (this is a W=1 build): > # https://github.com/intel-lab-lkp/linux/commit/c40ca148e9cff1a1c32cd4c5c9b252bf0cf201b6 > git remote add linux-review https://github.com/intel-lab-lkp/linux > git fetch --no-tags linux-review Terry-Bowman/cxl-pci-Add-RCH-downstream-port-AER-and-RAS-register-discovery/20230324-054044 > git checkout c40ca148e9cff1a1c32cd4c5c9b252bf0cf201b6 > # save the config file > mkdir build_dir && cp config build_dir/.config > make W=1 O=build_dir ARCH=i386 olddefconfig > make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/ > > If you fix the issue, kindly add following tag where applicable > | Reported-by: kernel test robot <lkp@intel.com> > | Link: https://lore.kernel.org/oe-kbuild-all/202303241458.BV292BDH-lkp@intel.com/ > > All errors (new ones prefixed by >>): > > drivers/cxl/mem.c: In function 'rcec_enable_aer_ints': >>> drivers/cxl/mem.c:51:36: error: 'struct pci_dev' has no member named 'rcec' > 51 | struct pci_dev *rcec = pdev->rcec; > | ^~ >>> drivers/cxl/mem.c:63:21: error: 'struct pci_dev' has no member named 'aer_cap'; did you mean 'ats_cap'? > 63 | aer = rcec->aer_cap; > | ^~~~~~~ > | ats_cap > > > vim +51 drivers/cxl/mem.c > > 48 > 49 static int rcec_enable_aer_ints(struct pci_dev *pdev) > 50 { > > 51 struct pci_dev *rcec = pdev->rcec; > 52 int aer, rc; > 53 u32 mask; > 54 > 55 if (!rcec) > 56 return -ENODEV; > 57 > 58 /* > 59 * Internal errors are masked by default, unmask RCEC's here > 60 * PCI6.0 7.8.4.3 Uncorrectable Error Mask Register (Offset 08h) > 61 * PCI6.0 7.8.4.6 Correctable Error Mask Register (Offset 14h) > 62 */ > > 63 aer = rcec->aer_cap; > 64 rc = pci_read_config_dword(rcec, aer + PCI_ERR_UNCOR_MASK, &mask); > 65 if (rc) > 66 return rc; > 67 mask &= ~PCI_ERR_UNC_INTN; > 68 rc = pci_write_config_dword(rcec, aer + PCI_ERR_UNCOR_MASK, mask); > 69 if (rc) > 70 return rc; > 71 > 72 rc = pci_read_config_dword(rcec, aer + PCI_ERR_COR_MASK, &mask); > 73 if (rc) > 74 return rc; > 75 mask &= ~PCI_ERR_COR_INTERNAL; > 76 rc = pci_write_config_dword(rcec, aer + PCI_ERR_COR_MASK, mask); > 77 > 78 return rc; > 79 } > 80 >
I will add #ifdef checks for CONFIG_PCIEPORTBUS and CONFIG_PCIEAER around the related code.
Regards, Terry
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