Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [PATCH v3 4/8] x86/psp: Add IRQ support | Date | Tue, 21 Mar 2023 11:31:18 +0100 |
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On Mon, Mar 20 2023 at 19:19, Jeremi Piotrowski wrote: > The ACPI PSP device provides a mailbox irq that needs to be configured > through the ACPI mailbox register first. This requires passing a CPU > vector and physical CPU id and then enabling interrupt delivery. > Allocate the irq directly from the default irq domain > (x86_vector_domain) to get access to the required information. By > passing a cpumask through irq_alloc_info the vector is immediately > allocated (and not later during activation) and can be retrieved.
Sorry, but this is a horrible hack which violates _all_ design rules for interrupts in one go.
1) What's so special about this PSP device that it requires a vector directly from the vector domain and evades interrupt remapping?
2) Why is this interrupt enabled _before_ it is actually requested?
3) Why is this interrupt required to be bound to CPU0 and still exposes a disfunctional and broken affinity setter interface in /proc?
There is absolutely zero reason and justification to fiddle in the guts of the x86 vector configuration data just because it's possible.
This is clearly a custom MSI implementation and the obvious solution is a per device MSI interrupt domain.
Thanks,
tglx
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