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    SubjectRe: [PATCH v1 14/14] iommu/arm-smmu-v3: Add arm_smmu_cache_invalidate_user
    On Mon, Mar 20, 2023 at 08:56:00AM -0700, Nicolin Chen wrote:
    > On Mon, Mar 20, 2023 at 10:03:04AM -0300, Jason Gunthorpe wrote:
    > > On Sat, Mar 11, 2023 at 03:56:50AM -0800, Nicolin Chen wrote:
    > >
    > > > I recall that one difficulty is to pass the vSID from the guest
    > > > down to the host kernel driver and to link with the pSID. What I
    > > > did previously for VCMDQ was to set the SID_MATCH register with
    > > > iommu_group_id(group) and set the SID_REPLACE register with the
    > > > pSID. Then hyper will use the iommu_group_id to search for the
    > > > pair of the registers, and to set vSID. Perhaps we should think
    > > > of something smarter.
    > >
    > > We need an ioctl for this, I think. To load a map of vSID to dev_id
    > > into the driver. Kernel will convert dev_id to pSID. Driver will
    > > program the map into HW.
    >
    > Can we just pass a vSID via the alloc ioctl like this?
    >
    > -----------------------------------------------------------
    > @@ -429,7 +429,7 @@ struct iommu_hwpt_arm_smmuv3 {
    > #define IOMMU_SMMUV3_FLAG_VMID (1 << 1) /* vmid override */
    > __u64 flags;
    > __u32 s2vmid;
    > - __u32 __reserved;
    > + __u32 sid;
    > __u64 s1ctxptr;
    > __u64 s1cdmax;
    > __u64 s1fmt;
    > -----------------------------------------------------------
    >
    > An alloc is initiated by an SMMU_CMD_CFGI_STE command that has
    > an SID filed anyway.

    No, a HWPT is not a device or a SID. a HWPT is an ASID in the ARM
    model.

    dev_id is the SID.

    The cfgi_ste will carry the vSID which is mapped to a iommufd dev_id.

    The kernel has to translate the vSID to the dev_id to the pSID to
    issue an ATC invalidation for the correct entity.

    > > SW path will program the map into an xarray
    >
    > I found a tricky thing about SIDs in the SMMU driver when doing
    > this experiment: the SMMU kernel driver mostly handles devices
    > using struct arm_smmu_master. However, an arm_smmu_master might
    > have a num_streams>1, meaning a device can have multiple SIDs.
    > Though it seems that PCI devices might not be in this scope, a
    > plain xarray might not work for other type of devices in a long
    > run, if there'd be?

    You'd replicate each of the vSIDs of the extra SIDs in the xarray.

    > > > cache_invalidate_user as void, like we are doing now? An fault
    > > > injection pathway to report CERROR asynchronously is what we've
    > > > been doing though -- even with Eric's previous VFIO solution.
    > >
    > > Where is this? How does it look?
    >
    > That's postponed with the PRI support, right? My use case does
    > not need PRI actually, but a fault injection pathway to guests.
    > This pathway should be able to take care of any CERROR (detected
    > by a host interrupt) or something funky in cache_invalidate_user
    > requests itself?

    I would expect that if invalidation can fail that we have a way to
    signal that failure back to the guest.

    Jason

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