Messages in this thread | | | From | Martin Blumenstingl <> | Date | Mon, 20 Mar 2023 16:35:50 +0100 | Subject | Re: [PATCH V2] clk: meson: vid-pll-div: added meson_vid_pll_div_ops support |
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Hello Yu Tu,
On Mon, Mar 20, 2023 at 12:35 PM Yu Tu <yu.tu@amlogic.com> wrote: > > Since the previous code only provides "ro_ops" for the vid_pll_div > clock. In fact, the clock can be set. So add "ops" that can set the > clock, especially for later chips like S4 SOC and so on. > > Signed-off-by: Yu Tu <yu.tu@amlogic.com> > --- please describe the changes you did compared to the previous version(s)
[...] > diff --git a/drivers/clk/meson/vid-pll-div.h b/drivers/clk/meson/vid-pll-div.h > index c0128e33ccf9..bbccab340910 100644 > --- a/drivers/clk/meson/vid-pll-div.h > +++ b/drivers/clk/meson/vid-pll-div.h > @@ -10,11 +10,14 @@ > #include <linux/clk-provider.h> > #include "parm.h" > > +#define VID_PLL_DIV_TABLE_SIZE 14 In v1 you used ARRAY_SIZE(vid_pll_div_table) wherever this new macro is used instead. I think using ARRAY_SIZE is the better approach because it means the references will update automatically if an entry is added/removed from vid_pll_div_table
Also I think there's a different understanding about what Jerome previously wrote: > It would be nice to actually describe how this vid pll work so we can > stop using precompute "magic" values and actually use the IP to its full > capacity. From what I understand is that you interpreted this as "let's change ARRAY_SIZE(vid_pll_div_table) to a new macro called VID_PLL_DIV_TABLE_SIZE". But I think what Jerome meant is: "let's get rid of vid_pll_div_table and implement how to actually calculate the clock rate - without hard-coding 14 possible clock settings in vid_pll_div_table". Look at clk-mpll.c and/or clk-pll.c which allow calculating arbitrary rates without any hard-coded tables.
Best regards, Martin
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