Messages in this thread | | | Subject | Re: [PATCH V4] LoongArch: Make WriteCombine configurable for ioremap() | From | Xi Ruoyao <> | Date | Mon, 20 Mar 2023 15:57:24 +0800 |
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On Thu, 2023-03-16 at 14:41 +0800, Huacai Chen wrote: > LoongArch maintains cache coherency in hardware, but when paired with > LS7A chipsets the WUC attribute (Weak-ordered UnCached, which is similar > to WriteCombine) is out of the scope of cache coherency machanism for > PCIe devices (this is a PCIe protocol violation, which may be fixed in > newer chipsets). > > This means WUC can only used for write-only memory regions now, so this > option is disabled by default, making WUC silently fallback to SUC for > ioremap(). You can enable this option if the kernel is ensured to run on > hardware without this bug. > > Kernel parameter writecombine=on/off can be used to override the Kconfig > option. > > Suggested-by: WANG Xuerui <kernel@xen0n.name> > Reviewed-by: WANG Xuerui <kernel@xen0n.name> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
LGTM.
I still prefer an automatic way, but anyway we can implement it later after a bug-free LS7A successor is launched.
Should we Cc: stable@vger.kernel.org and make a PR for 6.3 as well? To me it's a "bug fix" and needed for stable releases, but I'm not sure.
-- Xi Ruoyao <xry111@xry111.site> School of Aerospace Science and Technology, Xidian University
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