Messages in this thread | | | Date | Mon, 20 Mar 2023 11:54:25 +0800 | Subject | Re: [PATCH v2 3/6] dt-bindings: soc: starfive: syscon: Add optional patternProperties | From | Xingyu Wu <> |
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On 2023/3/19 20:28, Krzysztof Kozlowski wrote: > On 16/03/2023 04:05, Xingyu Wu wrote: >> Add optional compatible and patternProperties. >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> >> --- >> .../soc/starfive/starfive,jh7110-syscon.yaml | 39 ++++++++++++++++--- >> 1 file changed, 33 insertions(+), 6 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >> index ae7f1d6916af..b61d8921ef42 100644 >> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >> @@ -15,16 +15,31 @@ description: | >> >> properties: >> compatible: >> - items: >> - - enum: >> - - starfive,jh7110-aon-syscon >> - - starfive,jh7110-stg-syscon >> - - starfive,jh7110-sys-syscon >> - - const: syscon >> + oneOf: >> + - items: >> + - enum: >> + - starfive,jh7110-aon-syscon >> + - starfive,jh7110-stg-syscon >> + - starfive,jh7110-sys-syscon >> + - const: syscon >> + - items: >> + - enum: >> + - starfive,jh7110-aon-syscon >> + - starfive,jh7110-stg-syscon >> + - starfive,jh7110-sys-syscon >> + - const: syscon >> + - const: simple-mfd >> >> reg: >> maxItems: 1 >> >> +patternProperties: >> + # Optional children >> + "pll-clock-controller": > > It's not a pattern.
Does it use 'properties' instead of 'patternProperties'?
> > Anyway should be clock-controller
Will fix.
> >> + type: object >> + $ref: /schemas/clock/starfive,jh7110-pll.yaml# >> + description: Clock provider for PLL. >> + > > You just added these bindings! So the initial submission was incomplete > on purpose? > > No, add complete bindings.
Does you mean that it should drop the 'description', or add complete 'description', or add 'compatible', 'clocks' and 'clock-cells' of complete clock-controller bindings?
> >> required: >> - compatible >> - reg >> @@ -38,4 +53,16 @@ examples: >> reg = <0x10240000 0x1000>; >> }; >> >> + - | >> + syscon@13030000 { > > No need for new example... Just put it in existing one. >
Actually, the PLL clock-controller are just set in sys-syscon resgisters. The stg-syscon and aon-syscon don't need it. So PLL clock-controller node only is added in sys-syscon node.
Best regards, Xingyu Wu
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