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SubjectRe: [PATCH v2 1/6] dt-bindings: clock: Add StarFive JH7110 PLL clock generator
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On 2023/3/19 20:25, Krzysztof Kozlowski wrote:
> On 16/03/2023 04:05, Xingyu Wu wrote:
>> Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>
>
>> +
>> +examples:
>> + - |
>> + pllclk: pll-clock-controller {
>
> This should be just "clock-controller" (and drop the label).

Will modify to "clock-controller" and drop the label.
Thanks.

>
> With above
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>

Best regards,
Xingyu Wu

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