Messages in this thread | | | Date | Thu, 16 Mar 2023 20:34:05 +0100 | Subject | Re: [PATCH 1/3] dt-bindings: clock: qcom: Add bindings for videocc on SM8450 | From | Krzysztof Kozlowski <> |
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On 16/03/2023 09:30, Taniya Das wrote: > Add device tree bindings for the video clock controller on Qualcomm > SM8450 platform.
Subject: drop second/last, redundant "bindings for". The "dt-bindings" prefix is already stating that these are bindings.
> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > .../bindings/clock/qcom,sm8450-videocc.yaml | 84 +++++++++++++++++++ > .../dt-bindings/clock/qcom,videocc-sm8450.h | 38 +++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8450.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > new file mode 100644 > index 000000000000..909da704c123 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > @@ -0,0 +1,84 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Video Clock & Reset Controller on SM8450 > + > +maintainers: > + - Taniya Das <quic_tdas@quicinc.com> > + > +description: | > + Qualcomm video clock control module provides the clocks, resets and power > + domains on SM8450. > + > + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h > + > +properties: > + compatible: > + const: qcom,sm8450-videocc > + > + clocks: > + items: > + - description: Video AHB clock from GCC > + - description: Board XO source > + > + clock-names: > + items: > + - const: iface > + - const: bi_tcxo > + > + power-domains: > + maxItems: 1 > + description: > + A phandle and PM domain specifier for the MMCX power domain.
Drop "A phandle and PM domain specifier for the"
> + > + required-opps: > + maxItems: 1 > + description: > + A phandle to an OPP node describing required MMCX performance point. > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > + reg: > + maxItems: 1
That's a unusual ordering. Either order elements by name or use some custom order... but then reg is always second property.
> + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + - required-opps > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells'
And keep same order in required.
> + > +additionalProperties: false
Best regards, Krzysztof
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