Messages in this thread | | | Date | Tue, 14 Mar 2023 15:27:28 +0800 | From | Dylan Jhong <> | Subject | Re: [PATCH v2] riscv: mm: Fix incorrect ASID argument when flushing TLB |
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On Tue, Mar 14, 2023 at 10:22:43AM +0800, Zong Li wrote: > Dylan Jhong <dylan@andestech.com> 於 2023年3月13日 週一 下午12:29寫道: > > > > Currently, we pass the CONTEXTID instead of the ASID to the TLB flush > > function. We should only take the ASID field to prevent from touching > > the reserved bit field. > > > > Fixes: 3f1e782998cd ("riscv: add ASID-based tlbflushing methods") > > Signed-off-by: Dylan Jhong <dylan@andestech.com> > > --- > > Hi Dylan, > Thanks for your patch, if I remember correctly, there was a patch from > Alistair Francis did the similar fix. Perhaps we should track that > patch to see why it doesn't be merged. Thanks. > > http://lists.infradead.org/pipermail/linux-riscv/2022-March/013558.html > Hi Zong, Thanks for the reminder, I didn't notice that Alistair had sent the same patch before.
Hi Palmer, Alistair http://lists.infradead.org/pipermail/linux-riscv/2022-March/013597.html This patch does not seem to be cherry-picked back to the released linux kernel, and I have not seen the v4 patch. May I ask how is the follow-up progress of this patch?
Best, Dylan
> > Changes from v2: > > - Remove unsued EXPORT_SYMBOL() > > --- > > arch/riscv/include/asm/tlbflush.h | 2 ++ > > arch/riscv/mm/context.c | 2 +- > > arch/riscv/mm/tlbflush.c | 2 +- > > 3 files changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > > index 907b9efd39a8..597d6d8aec28 100644 > > --- a/arch/riscv/include/asm/tlbflush.h > > +++ b/arch/riscv/include/asm/tlbflush.h > > @@ -12,6 +12,8 @@ > > #include <asm/errata_list.h> > > > > #ifdef CONFIG_MMU > > +extern unsigned long asid_mask; > > + > > static inline void local_flush_tlb_all(void) > > { > > __asm__ __volatile__ ("sfence.vma" : : : "memory"); > > diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c > > index 80ce9caba8d2..6d1aeb063e81 100644 > > --- a/arch/riscv/mm/context.c > > +++ b/arch/riscv/mm/context.c > > @@ -22,7 +22,7 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); > > > > static unsigned long asid_bits; > > static unsigned long num_asids; > > -static unsigned long asid_mask; > > +unsigned long asid_mask; > > > > static atomic_long_t current_version; > > > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > > index ce7dfc81bb3f..ba4c27187c95 100644 > > --- a/arch/riscv/mm/tlbflush.c > > +++ b/arch/riscv/mm/tlbflush.c > > @@ -27,7 +27,7 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, > > /* check if the tlbflush needs to be sent to other CPUs */ > > broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > > if (static_branch_unlikely(&use_asid_allocator)) { > > - unsigned long asid = atomic_long_read(&mm->context.id); > > + unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask; > > > > /* > > * TLB will be immediately flushed on harts concurrently > > -- > > 2.34.1 > >
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