Messages in this thread | | | Date | Wed, 8 Feb 2023 18:02:43 +0100 | From | Johan Hovold <> | Subject | Re: [PATCH v8 11/11] arm64: dts: qcom: sm8550: Fix PCIe PHYs and controllers nodes |
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On Mon, Feb 06, 2023 at 11:26:19PM +0200, Abel Vesa wrote: > First, move the pinctrl related propeties out from SoC dtsi and into the > board dts and add blank lines before status properties in the PHY nodes > to be consistent with the rest of the nodes. Then drop the pipe clock > from the controller nodes. Rename the aggre0 and aggre1 clocks to more > generic noc_aggr. Add the cpu-pcie interconnects to both controller nodes. > Rename the pcie1 second reset to link_down and drop the unnecessary > enable-gpios. Switch the aux clock to GCC_PCIE_1_PHY_AUX_CLK for the pcie1 > PHY and drop the aux_phy from clock-names. Also rename the nocsr reset to > phy_nocsr. With this changes we are now in line with the SC8280XP bindings. > > Fixes: 98a4dc3a78fa ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > > This time, this patch actually fixes the already merged PCIe related > nodes. When compared to the earlier version of this patchset, this patch > leads to the PCIe nodes looking the same. Sorry for all this mess.
Looks good now.
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
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