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    Subject[PATCH net-next v3 2/3] net: dsa: rzn1-a5psw: add support for .port_bridge_flags
    Date
    When running vlan test (bridge_vlan_aware/unaware.sh), there were some
    failure due to the lack .port_bridge_flag function to disable port
    flooding. Implement this operation for BR_LEARNING, BR_FLOOD,
    BR_MCAST_FLOOD and BR_BCAST_FLOOD.

    Signed-off-by: Clément Léger <clement.leger@bootlin.com>
    ---
    drivers/net/dsa/rzn1_a5psw.c | 45 ++++++++++++++++++++++++++++++++++++
    1 file changed, 45 insertions(+)

    diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c
    index 8b7d4a371f8b..0ce3948952db 100644
    --- a/drivers/net/dsa/rzn1_a5psw.c
    +++ b/drivers/net/dsa/rzn1_a5psw.c
    @@ -342,6 +342,49 @@ static void a5psw_port_bridge_leave(struct dsa_switch *ds, int port,
    a5psw->br_dev = NULL;
    }

    +static int a5psw_port_pre_bridge_flags(struct dsa_switch *ds, int port,
    + struct switchdev_brport_flags flags,
    + struct netlink_ext_ack *extack)
    +{
    + if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
    + BR_BCAST_FLOOD))
    + return -EINVAL;
    +
    + return 0;
    +}
    +
    +static int
    +a5psw_port_bridge_flags(struct dsa_switch *ds, int port,
    + struct switchdev_brport_flags flags,
    + struct netlink_ext_ack *extack)
    +{
    + struct a5psw *a5psw = ds->priv;
    + u32 val;
    +
    + if (flags.mask & BR_LEARNING) {
    + val = flags.val & BR_LEARNING ? 0 : A5PSW_INPUT_LEARN_DIS(port);
    + a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN,
    + A5PSW_INPUT_LEARN_DIS(port), val);
    + }
    +
    + if (flags.mask & BR_FLOOD) {
    + val = flags.val & BR_FLOOD ? BIT(port) : 0;
    + a5psw_reg_rmw(a5psw, A5PSW_UCAST_DEF_MASK, BIT(port), val);
    + }
    +
    + if (flags.mask & BR_MCAST_FLOOD) {
    + val = flags.val & BR_MCAST_FLOOD ? BIT(port) : 0;
    + a5psw_reg_rmw(a5psw, A5PSW_MCAST_DEF_MASK, BIT(port), val);
    + }
    +
    + if (flags.mask & BR_BCAST_FLOOD) {
    + val = flags.val & BR_BCAST_FLOOD ? BIT(port) : 0;
    + a5psw_reg_rmw(a5psw, A5PSW_BCAST_DEF_MASK, BIT(port), val);
    + }
    +
    + return 0;
    +}
    +
    static void a5psw_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
    {
    u32 mask = A5PSW_INPUT_LEARN_DIS(port) | A5PSW_INPUT_LEARN_BLOCK(port);
    @@ -754,6 +797,8 @@ static const struct dsa_switch_ops a5psw_switch_ops = {
    .set_ageing_time = a5psw_set_ageing_time,
    .port_bridge_join = a5psw_port_bridge_join,
    .port_bridge_leave = a5psw_port_bridge_leave,
    + .port_pre_bridge_flags = a5psw_port_pre_bridge_flags,
    + .port_bridge_flags = a5psw_port_bridge_flags,
    .port_stp_state_set = a5psw_port_stp_state_set,
    .port_fast_age = a5psw_port_fast_age,
    .port_fdb_add = a5psw_port_fdb_add,
    --
    2.39.0
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