Messages in this thread | | | Subject | Re: [PATCH v2 2/5] LoongArch: Use la.pcrel instead of la.abs for exception handlers | From | Jinyang He <> | Date | Wed, 8 Feb 2023 08:59:19 +0800 |
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On 2023-02-07 22:39, Xi Ruoyao wrote: > On Tue, 2023-02-07 at 22:28 +0800, Xi Ruoyao wrote: >> +struct handler_reloc *eentry_reloc[128] = { >> + [0] = NULL, /* merr handler */ > Self review: > > This is actually incorrect. Currently the merr handler (except_vec_cex) > is coded as: > > SYM_FUNC_START(except_vec_cex) > b cache_parity_error > SYM_FUNC_END(except_vec_cex) > > Once this is copied into the per-cpu handler page, the offset (coded in > the b instruction) will be absolutely wrong. But it's already incorrect > in the current mainline, and I'm not familiar with CSR.CRMD.DA=1 > configuration so I'm not sure how to fix it. > It bothers me, too. And I've mentioned it to Huacai offline before. Besides, after fixing this issue I'll support a series of patches to fix the cfi note in asm files.
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