Messages in this thread | | | Date | Mon, 27 Feb 2023 12:55:57 -0600 | From | Rob Herring <> | Subject | Re: [PATCH v3 4/7] dt-bindings: PCI: dwc: add DMA, region mask bits |
| |
On Thu, Feb 23, 2023 at 08:05:28PM +0200, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Add properties to support configurable DMA mask bits > and region mask bits. > configurable DMA mask bits is needed for Marvell AC5/AC5X SOCs which > have their physical DDR memory start at address 0x2_0000_0000. > Configurable region mask bits is needed for the Marvell Armada > 7020/7040/8040 SOCs when the DT file places the PCIe window above the > 4GB region. > The Synopsis Designware PCIe IP in these SOCs is too old to specify the > highest memory location supported by the PCIe, but practically supports > such locations. Allow these locations to be specified in the DT file. > First DT property is called num-dmamask, > and can range between 33 and 64. > Second DT property is called num-regionmask, > and can range between 33 and 64. > > Signed-off-by: Elad Nachman <enachman@marvell.com> > --- > .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > index d87e13496834..a1b06ff19ca7 100644 > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > @@ -261,6 +261,16 @@ properties: > > dma-coherent: true > > + num-dmamask:
Nope! There's already a defined way to define DMA/bus addresses and sizes in DT. That's dma-ranges.
Rob
| |