Messages in this thread | | | Date | Mon, 27 Feb 2023 18:01:00 +0100 | Subject | Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE | From | David Hildenbrand <> |
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>>>> /* >>>> * Externally used page protection values. >>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h >>>> index 42f5988e998b..7e3de54bf426 100644 >>>> --- a/arch/microblaze/include/asm/pgtable.h >>>> +++ b/arch/microblaze/include/asm/pgtable.h >>>> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address); >>>> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB >>>> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct >>>> * zone. >>>> - * - PRESENT *must* be in the bottom two bits because swap cache >>>> - * entries use the top 30 bits. Because 4xx doesn't support SMP >>>> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 >>>> - * is cleared in the TLB miss handler before the TLB entry is loaded. >>>> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top >>>> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we >>>> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler >>>> + * before the TLB entry is loaded. >>> >>> So the PowerPC 4xx comment is still here? >> >> I only dropped the comment above __swp_type(). I guess you mean that we >> could also drop the "Because 4xx doesn't support SMP anyway, M is >> irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not > > Yes, that's what I meant. > >> sure about the "Bit 30 is cleared in the TLB miss handler" comment, if >> that can similarly be dropped. > > No idea, didn't check. But if it was copied from PPC, chances are > high it's no longer true....
I'll have a look.
> >>>> * - All other bits of the PTE are loaded into TLBLO without >>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for >>>> * software PTE bits. We actually use bits 21, 24, 25, and >>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); >>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ >>>> #define _PMD_PRESENT PAGE_MASK >>>> >>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY >>> >>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is >>> wrong? >> >> In the example, I use MSB-0 bit numbering (which I determined to be >> correct in microblaze context eventually, but I got confused a couple a >> times because it's very inconsistent). That should be MSB-0 bit 24. > > Thanks, TIL microblaze uses IBM bit numbering...
I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct?
I recall that I used the comment above "/* Definitions for MicroBlaze. */" as an orientation.
0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RPN..................... 0 0 EX WR ZSEL....... W I M G
So ... either we adjust both or we leave it as is. (again, depends on what the right thing to to is -- which I don't know :) )
-- Thanks,
David / dhildenb
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