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    Subject[PATCH v12 046/106] KVM: TDX: Add accessors VMX VMCS helpers
    Date
    From: Sean Christopherson <sean.j.christopherson@intel.com>

    TDX defines SEAMCALL APIs to access TDX control structures corresponding to
    the VMX VMCS. Introduce helper accessors to hide its SEAMCALL ABI details.

    Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
    ---
    arch/x86/kvm/vmx/tdx.h | 95 ++++++++++++++++++++++++++++++++++++++++++
    1 file changed, 95 insertions(+)

    diff --git a/arch/x86/kvm/vmx/tdx.h b/arch/x86/kvm/vmx/tdx.h
    index 5fa4d3198873..7c8f5880d104 100644
    --- a/arch/x86/kvm/vmx/tdx.h
    +++ b/arch/x86/kvm/vmx/tdx.h
    @@ -57,6 +57,101 @@ static inline struct vcpu_tdx *to_tdx(struct kvm_vcpu *vcpu)
    return container_of(vcpu, struct vcpu_tdx, vcpu);
    }

    +static __always_inline void tdvps_vmcs_check(u32 field, u8 bits)
    +{
    +#define VMCS_ENC_ACCESS_TYPE_MASK 0x1UL
    +#define VMCS_ENC_ACCESS_TYPE_FULL 0x0UL
    +#define VMCS_ENC_ACCESS_TYPE_HIGH 0x1UL
    +#define VMCS_ENC_ACCESS_TYPE(field) ((field) & VMCS_ENC_ACCESS_TYPE_MASK)
    +
    + /* TDX is 64bit only. HIGH field isn't supported. */
    + BUILD_BUG_ON_MSG(__builtin_constant_p(field) &&
    + VMCS_ENC_ACCESS_TYPE(field) == VMCS_ENC_ACCESS_TYPE_HIGH,
    + "Read/Write to TD VMCS *_HIGH fields not supported");
    +
    + BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64);
    +
    +#define VMCS_ENC_WIDTH_MASK GENMASK(14, 13)
    +#define VMCS_ENC_WIDTH_16BIT (0UL << 13)
    +#define VMCS_ENC_WIDTH_64BIT (1UL << 13)
    +#define VMCS_ENC_WIDTH_32BIT (2UL << 13)
    +#define VMCS_ENC_WIDTH_NATURAL (3UL << 13)
    +#define VMCS_ENC_WIDTH(field) ((field) & VMCS_ENC_WIDTH_MASK)
    +
    + /* TDX is 64bit only. i.e. natural width = 64bit. */
    + BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) &&
    + (VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_64BIT ||
    + VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_NATURAL),
    + "Invalid TD VMCS access for 64-bit field");
    + BUILD_BUG_ON_MSG(bits != 32 && __builtin_constant_p(field) &&
    + VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_32BIT,
    + "Invalid TD VMCS access for 32-bit field");
    + BUILD_BUG_ON_MSG(bits != 16 && __builtin_constant_p(field) &&
    + VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_16BIT,
    + "Invalid TD VMCS access for 16-bit field");
    +}
    +
    +static __always_inline void tdvps_state_non_arch_check(u64 field, u8 bits) {}
    +static __always_inline void tdvps_management_check(u64 field, u8 bits) {}
    +
    +#define TDX_BUILD_TDVPS_ACCESSORS(bits, uclass, lclass) \
    +static __always_inline u##bits td_##lclass##_read##bits(struct vcpu_tdx *tdx, \
    + u32 field) \
    +{ \
    + struct tdx_module_output out; \
    + u64 err; \
    + \
    + tdvps_##lclass##_check(field, bits); \
    + err = tdh_vp_rd(tdx->tdvpr_pa, TDVPS_##uclass(field), &out); \
    + if (KVM_BUG_ON(err, tdx->vcpu.kvm)) { \
    + pr_err("TDH_VP_RD["#uclass".0x%x] failed: 0x%llx\n", \
    + field, err); \
    + return 0; \
    + } \
    + return (u##bits)out.r8; \
    +} \
    +static __always_inline void td_##lclass##_write##bits(struct vcpu_tdx *tdx, \
    + u32 field, u##bits val) \
    +{ \
    + struct tdx_module_output out; \
    + u64 err; \
    + \
    + tdvps_##lclass##_check(field, bits); \
    + err = tdh_vp_wr(tdx->tdvpr_pa, TDVPS_##uclass(field), val, \
    + GENMASK_ULL(bits - 1, 0), &out); \
    + if (KVM_BUG_ON(err, tdx->vcpu.kvm)) \
    + pr_err("TDH_VP_WR["#uclass".0x%x] = 0x%llx failed: 0x%llx\n", \
    + field, (u64)val, err); \
    +} \
    +static __always_inline void td_##lclass##_setbit##bits(struct vcpu_tdx *tdx, \
    + u32 field, u64 bit) \
    +{ \
    + struct tdx_module_output out; \
    + u64 err; \
    + \
    + tdvps_##lclass##_check(field, bits); \
    + err = tdh_vp_wr(tdx->tdvpr_pa, TDVPS_##uclass(field), bit, bit, &out); \
    + if (KVM_BUG_ON(err, tdx->vcpu.kvm)) \
    + pr_err("TDH_VP_WR["#uclass".0x%x] |= 0x%llx failed: 0x%llx\n", \
    + field, bit, err); \
    +} \
    +static __always_inline void td_##lclass##_clearbit##bits(struct vcpu_tdx *tdx, \
    + u32 field, u64 bit) \
    +{ \
    + struct tdx_module_output out; \
    + u64 err; \
    + \
    + tdvps_##lclass##_check(field, bits); \
    + err = tdh_vp_wr(tdx->tdvpr_pa, TDVPS_##uclass(field), 0, bit, &out); \
    + if (KVM_BUG_ON(err, tdx->vcpu.kvm)) \
    + pr_err("TDH_VP_WR["#uclass".0x%x] &= ~0x%llx failed: 0x%llx\n", \
    + field, bit, err); \
    +}
    +
    +TDX_BUILD_TDVPS_ACCESSORS(16, VMCS, vmcs);
    +TDX_BUILD_TDVPS_ACCESSORS(32, VMCS, vmcs);
    +TDX_BUILD_TDVPS_ACCESSORS(64, VMCS, vmcs);
    +
    static __always_inline u64 td_tdcs_exec_read64(struct kvm_tdx *kvm_tdx, u32 field)
    {
    struct tdx_module_output out;
    --
    2.25.1
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      Last update: 2023-03-27 00:36    [W:4.046 / U:0.044 seconds]
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