Messages in this thread | | | From | Krishna Yarlagadda <> | Subject | RE: [PATCH] spi: tegra210-quad: Fix iterator outside loop | Date | Fri, 24 Feb 2023 16:50:00 +0000 |
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> -----Original Message----- > From: Mark Brown <broonie@kernel.org> > Sent: 24 February 2023 22:17 > To: Krishna Yarlagadda <kyarlagadda@nvidia.com> > Cc: linux-spi@vger.kernel.org; linux-tegra@vger.kernel.org; linux- > kernel@vger.kernel.org; thierry.reding@gmail.com; Jonathan Hunter > <jonathanh@nvidia.com>; Sowjanya Komatineni > <skomatineni@nvidia.com>; Laxman Dewangan <ldewangan@nvidia.com> > Subject: Re: [PATCH] spi: tegra210-quad: Fix iterator outside loop > > On Fri, Feb 24, 2023 at 10:05:13PM +0530, Krishna Yarlagadda wrote: > > > msg->actual_length += xfer->len; > > + if (!xfer->cs_change && transfer_phase == DATA_TRANSFER) > { > > + tegra_qspi_transfer_end(spi); > > + spi_transfer_delay_exec(xfer); > > + } > > transfer_phase++; > > } > > - if (!xfer->cs_change) { > > - tegra_qspi_transfer_end(spi); > > - spi_transfer_delay_exec(xfer); > > - } > > This looks like it'll do the wrong thing and do a change on every > transfer if cs_change isn't set? This condition is hit only in data phase which is end of message. KY
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