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    Subject[RFC PATCH v3 12/32] x86/cpu: add MSR numbers for FRED configuration
    Date
    From: "H. Peter Anvin (Intel)" <hpa@zytor.com>

    Add MSR numbers for the FRED configuration registers.

    Originally-by: Megha Dey <megha.dey@intel.com>
    Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
    Signed-off-by: Xin Li <xin3.li@intel.com>
    ---
    arch/x86/include/asm/msr-index.h | 13 ++++++++++++-
    tools/arch/x86/include/asm/msr-index.h | 13 ++++++++++++-
    2 files changed, 24 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
    index ad35355ee43e..87db728f8bbc 100644
    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -36,8 +36,19 @@
    #define EFER_FFXSR (1<<_EFER_FFXSR)
    #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)

    -/* Intel MSRs. Some also available on other CPUs */
    +/* FRED MSRs */
    +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */
    +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */
    +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */
    +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */
    +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */
    +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */
    +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */
    +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */
    +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */
    +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */

    +/* Intel MSRs. Some also available on other CPUs */
    #define MSR_TEST_CTRL 0x00000033
    #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
    #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
    diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
    index 37ff47552bcb..0ade66db3627 100644
    --- a/tools/arch/x86/include/asm/msr-index.h
    +++ b/tools/arch/x86/include/asm/msr-index.h
    @@ -34,8 +34,19 @@
    #define EFER_LMSLE (1<<_EFER_LMSLE)
    #define EFER_FFXSR (1<<_EFER_FFXSR)

    -/* Intel MSRs. Some also available on other CPUs */
    +/* FRED MSRs */
    +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */
    +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */
    +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */
    +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */
    +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */
    +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */
    +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */
    +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */
    +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */
    +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */

    +/* Intel MSRs. Some also available on other CPUs */
    #define MSR_TEST_CTRL 0x00000033
    #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
    #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
    --
    2.34.1
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