Messages in this thread | | | From | Krishna Yarlagadda <> | Subject | RE: [Patch V3 1/3] tpm_tis-spi: Support hardware wait polling | Date | Fri, 24 Feb 2023 14:16:27 +0000 |
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> -----Original Message----- > From: Mark Brown <broonie@kernel.org> > Sent: 24 February 2023 00:13 > To: Krishna Yarlagadda <kyarlagadda@nvidia.com> > Cc: robh+dt@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca; > jarkko@kernel.org; krzysztof.kozlowski+dt@linaro.org; linux- > spi@vger.kernel.org; linux-tegra@vger.kernel.org; linux- > integrity@vger.kernel.org; linux-kernel@vger.kernel.org; > thierry.reding@gmail.com; Jonathan Hunter <jonathanh@nvidia.com>; > Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan > <ldewangan@nvidia.com> > Subject: Re: [Patch V3 1/3] tpm_tis-spi: Support hardware wait polling > > On Thu, Feb 23, 2023 at 06:41:43PM +0000, Krishna Yarlagadda wrote: > > > > > + spi_bus_lock(phy->spi_device->master); > > > > + > > > > + while (len) { > > > > Why? > > > TPM supports max 64B in single transaction. Loop to send rest of it. > > No, why is there a bus lock? Bus lock to avoid other clients to be accessed between TPM transfers.
> > > > > + spi_xfer[0].tx_buf = phy->iobuf; > > > > + spi_xfer[0].len = 1; > > > > + spi_message_add_tail(&spi_xfer[0], &m); > > > > + > > > > + spi_xfer[1].tx_buf = phy->iobuf + 1; > > > > + spi_xfer[1].len = 3; > > > > + spi_message_add_tail(&spi_xfer[1], &m); > > > > Why would we make these two separate transfers? > > > Tegra QSPI combined sequence requires cmd, addr and data in different > > transfers. This eliminates need for additional flag for combined sequence. > > That needs some documentation, and we might need a flag to ensure the > core doesn't coalesce the transfers. Will add comment at top of the function. Bus lock should avoid coalesce of transfer of single message from others. KY
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