Messages in this thread Patch in this message | | | From | Ravi Gunasekaran <> | Subject | [PATCH v11 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI | Date | Fri, 24 Feb 2023 15:54:33 +0530 |
| |
From: Aswath Govindraju <a-govindraju@ti.com>
Add support for two instance of OSPI in J721S2 SoC.
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> --- Changes from v10: * Documented the reason for disabling the nodes by default. * Removed Link tag from commmit message
Changes from v9: * Disabled fss, ospi nodes by default in common DT file
Changes from v8: * Updated "ranges" property to fix dtbs warnings
Changes from v7: * Removed "reg" property from syscon node * Renamed the "syscon" node to "bus" to after change in compatible property
Changes from v6: * Fixed the syscon node's compatible property
Changes from v5: * Updated the syscon node's compatible property * Removed Cc tags from commit message
Changes from v4: * No change
Changes from v3: * No change
Changes from v2: * No change
Changes from v1: * No change
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..5005a3ebbd34 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,66 @@ ti,cpts-periodic-outputs = <2>; }; }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + /* + * Disable the node by default in the common include file. + * And enable it in the board specific DT file where the + * pinmux property is added. + */ + status = "disabled"; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 109 5>; + assigned-clocks = <&k3_clks 109 5>; + assigned-clock-parents = <&k3_clks 109 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Disable the node by default in the common include + * file. And enable it in the board specific DT file + * where the pinmux property is added. + */ + status = "disabled"; + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 110 5>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Disable the node by default in the common include + * file. And enable it in the board specific DT file + * where the pinmux property is added. + */ + status = "disabled"; + }; + + }; }; -- 2.17.1
| |