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    Subject[PATCH v2 13/16] arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain
    Date
    Similarly to what can be seen in MT8192, on MT8195 the mfg_core_tmp
    clock is a mux used to switch between different "safe" (and slower)
    clock sources for the GPU: this is used during MFGPLL reconfiguration
    and eventually during idling at very low frequencies.

    This clock getting turned off means that the GPU will occasionally be
    unclocked, producing obvious consequences such as system crash or
    unpredictable behavior: assigning it to the top level MFG power domain
    will make sure that this stays on at all times during any operation on
    the MFG domain (only GPU-related transactions).

    Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
    ---
    arch/arm64/boot/dts/mediatek/mt8195.dtsi | 5 +++--
    1 file changed, 3 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
    index 8fc527570791..6767bac3f69e 100644
    --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
    +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
    @@ -446,8 +446,9 @@ mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {

    power-domain@MT8195_POWER_DOMAIN_MFG1 {
    reg = <MT8195_POWER_DOMAIN_MFG1>;
    - clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
    - clock-names = "mfg";
    + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
    + <&topckgen CLK_TOP_MFG_CORE_TMP>;
    + clock-names = "mfg", "alt";
    mediatek,infracfg = <&infracfg_ao>;
    #address-cells = <1>;
    #size-cells = <0>;
    --
    2.39.2
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