Messages in this thread | | | From | Michael Ellerman <> | Subject | Re: [PATCH v2] arch/powerpc/include/asm/barrier.h: redefine rmb and wmb to lwsync | Date | Thu, 23 Feb 2023 20:24:34 +1100 |
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Kautuk Consul <kconsul@linux.vnet.ibm.com> writes: > >> You are correct, the patch is wrong because it fails to account for IO >> accesses. > > Okay, I looked at the PowerPC ISA and found: > "The memory barrier provides an ordering function for the storage accesses > caused by Load, Store,and dcbz instructions that are executed by the processor > executing the sync instruction and for which the specified storage location > is in storage that is Memory Coherence Required and is neither Write Through > Required nor Caching Inhibited.
Yep, that's the key sentence there. If you look at the definition for "sync" it has not exceptions for different storage types.
I agree it's not very clear unless you're looking closely.
> Thanks for your time, Michael. Sorry for the noise. >> >> Kautuk, I'm not sure what motivated you to look at these barriers, was >> it just the documentation you linked to?
> I read the basic documentation. Now that I have access to the PowerISA > document I guess I'll go through it more thoroughly.
The ISA is available publicly. There's links to most versions here:
https://wiki.raptorcs.com/wiki/Power_ISA
cheers
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