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SubjectRe: [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible
On Tue, Feb 21, 2023 at 10:46:42AM +0800, Hal Feng wrote:
> Add a new compatible string in cpu.yaml for SiFive S7 CPU
> core which is used on SiFive U74-MC core complex etc.
>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index a2884e3113da..54bfe24a436b 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -35,6 +35,7 @@ properties:
> - sifive,e7
> - sifive,e71
> - sifive,rocket0
> + - sifive,s7
> - sifive,u5
> - sifive,u54
> - sifive,u7
> --
> 2.38.1
>
>
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