Messages in this thread | | | Date | Fri, 17 Feb 2023 22:54:13 +0200 | Subject | Re: [PATCH v2 05/14] drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi | From | Dmitry Baryshkov <> |
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On 14/02/2023 19:31, Konrad Dybcio wrote: > These SKUs don't support the feature. Disable it to make the GPU stop > crashing after almost each and every submission - the received data on > the GPU end was simply incomplete in garbled, resulting in almost nothing > being executed properly. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 36f062c7582f..82757f005a1a 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -540,7 +540,13 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > config.rev.minor, config.rev.patchid); > > priv->is_a2xx = config.rev.core == 2; > - priv->has_cached_coherent = config.rev.core >= 6; > + > + if (config.rev.core >= 6) { > + /* Exclude A610 and A619_holi */ > + if (!(adreno_cmp_rev(ADRENO_REV(6, 1, 0, ANY_ID), config.rev) || > + adreno_cmp_rev(ADRENO_REV(6, 1, 9, 1), config.rev))) > + priv->has_cached_coherent = true; > + }
I'd suggest something like:
if (config.rev.core >= 6 && !(info.quirks & ADRENO_QUIRK_NO_CACHE_COHERENT)) priv->has_cache_coherent = true;
Let's keep all the information and quirks in a single place.
> > gpu = info->init(drm); > if (IS_ERR(gpu)) {
-- With best wishes Dmitry
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