Messages in this thread | | | Date | Thu, 16 Feb 2023 17:51:37 +0200 | Subject | Re: [PATCH 07/12] dt-bindings: net: Add StarFive JH7100 SoC | From | Cristian Ciocaltea <> |
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On 2/15/23 15:01, Andrew Lunn wrote: > On Wed, Feb 15, 2023 at 02:34:23AM +0200, Cristian Ciocaltea wrote: >> On 2/11/23 18:01, Andrew Lunn wrote: >>>> + starfive,gtxclk-dlychain: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + description: GTX clock delay chain setting >>> >>> Please could you add more details to this. Is this controlling the >>> RGMII delays? 0ns or 2ns? >> >> This is what gets written to JH7100_SYSMAIN_REGISTER49 and it's currently >> set to 4 in patch 12/12. As already mentioned, I don't have the register >> information in the datasheet, but I'll update this as soon as we get some >> details. > > I have seen what happens to this value, but i have no idea what it > actually means. And without knowing what it means, i cannot say if it > is being used correctly or not. And it could be related to the next > part of my comment... > >> >>>> + gmac: ethernet@10020000 { >>>> + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; >>>> + reg = <0x0 0x10020000 0x0 0x10000>; >>>> + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, >>>> + <&clkgen JH7100_CLK_GMAC_AHB>, >>>> + <&clkgen JH7100_CLK_GMAC_PTP_REF>, >>>> + <&clkgen JH7100_CLK_GMAC_GTX>, >>>> + <&clkgen JH7100_CLK_GMAC_TX_INV>; >>>> + clock-names = "stmmaceth", "pclk", "ptp_ref", "gtxc", "tx"; >>>> + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; >>>> + reset-names = "ahb"; >>>> + interrupts = <6>, <7>; >>>> + interrupt-names = "macirq", "eth_wake_irq"; >>>> + max-frame-size = <9000>; >>>> + phy-mode = "rgmii-txid"; >>> >>> This is unusual. Does your board have a really long RX clock line to >>> insert the 2ns delay needed on the RX side? >> >> Just tested with "rgmii" and didn't notice any issues. If I'm not missing >> anything, I'll do the change in the next revision. > > rgmii-id is generally the value to be used. That indicates the board > needs 2ns delays adding by something, either the MAC or the PHY. And > then i always recommend the MAC driver does nothing, pass the value to > the PHY and let the PHY add the delays. > > So try both rgmii and rgmii-id and do a lot of bi directional > transfers. Then look at the reported ethernet frame check sum error > counts, both local and the link peer. I would expect one setting gives > you lots of errors, and the other works much better.
I gave "rgmii-id" a try and it's not usable, I get too many errors. So "rgmii" should be the right choice here.
Thanks, Cristian
> Andrew >
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