Messages in this thread Patch in this message | | | From | Bartosz Golaszewski <> | Subject | [PATCH v3 3/9] arm64: dts: qcom: sa8775p: add the i2c18 node | Date | Thu, 16 Feb 2023 13:52:51 +0100 |
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From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add a disabled node for the I2C interface that's exposed on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 894c0662afb4..4666e5341922 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -502,6 +502,27 @@ qupv3_id_2: geniqup@8c0000 { clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0x5a3 0x0>; status = "disabled"; + + i2c18: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x890000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 + &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 + &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; intc: interrupt-controller@17a00000 { -- 2.37.2
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