Messages in this thread | | | From | Linus Torvalds <> | Date | Wed, 15 Feb 2023 15:22:35 -0800 | Subject | Re: [PATCH v2 0/8] x86/mtrr: fix handling with PAT but without MTRR |
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On Wed, Feb 15, 2023 at 12:25 AM Juergen Gross <jgross@suse.com> wrote: > > The problem arises in case a large mapping is spanning multiple MTRRs, > even if they define the same caching type (uniform is set to 0 in this > case).
Oh, I think then you should fix uniform to be 1.
IOW, we should not think "multiple MTRRs" means "non-uniform". Only "different actual memory types" should mean non-uniformity.
If I remember correctly, there were good reasons to have overlapping MTRR's. In fact, you can generate a single MTRR that described a memory ttype that wasn't even contiguous if you had odd memory setups.
Intel definitely defines how overlapping MTRR's work, and "same types overlaps" is documented as a real thing.
Linus
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