Messages in this thread | | | Date | Wed, 15 Feb 2023 22:09:12 +0000 | From | Conor Dooley <> | Subject | Re: [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA |
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On Mon, Feb 06, 2023 at 12:14:52PM -0800, Evan Green wrote:
> + case RISCV_HWPROBE_KEY_IMA_EXT_0: > + { > + u64 val = 0; > + > + if (has_fpu()) > + val |= RISCV_HWPROBE_IMA_FD;
The indent caught my eye here for a sec so my attention was drawn back here. Would you mind adding a line of whitespace between these checks? Cheers, Conor.
> + if (elf_hwcap & RISCV_ISA_EXT_c) > + val |= RISCV_HWPROBE_IMA_C; > + ret = set_hwprobe(pairs, val); > + } > + break; > +
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