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    Subject[PATCH v2 22/47] clk: mediatek: mt7622: Properly use CLK_IS_CRITICAL flag
    Date
    Instead of calling clk_prepare_enable() for clocks that shall stay
    enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that.

    Fixes: 2fc0a509e4ee ("clk: mediatek: add clock support for MT7622 SoC")
    Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
    ---
    drivers/clk/mediatek/clk-mt7622.c | 35 +++++++++++++------------------
    1 file changed, 15 insertions(+), 20 deletions(-)

    diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
    index 41af8d420bbf..1c0049fbeb69 100644
    --- a/drivers/clk/mediatek/clk-mt7622.c
    +++ b/drivers/clk/mediatek/clk-mt7622.c
    @@ -50,9 +50,9 @@
    _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
    NULL, "clkxtal")

    -#define GATE_APMIXED(_id, _name, _parent, _shift) \
    - GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, \
    - &mtk_clk_gate_ops_no_setclr_inv)
    +#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \
    + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \
    + &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL)

    #define GATE_INFRA(_id, _name, _parent, _shift) \
    GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
    @@ -66,6 +66,10 @@
    #define GATE_PERI0(_id, _name, _parent, _shift) \
    GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)

    +#define GATE_PERI0_AO(_id, _name, _parent, _shift) \
    + GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \
    + &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL)
    +
    #define GATE_PERI1(_id, _name, _parent, _shift) \
    GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)

    @@ -315,7 +319,7 @@ static const struct mtk_pll_data plls[] = {
    };

    static const struct mtk_gate apmixed_clks[] = {
    - GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
    + GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
    };

    static const struct mtk_gate infra_clks[] = {
    @@ -450,7 +454,7 @@ static const struct mtk_gate peri_clks[] = {
    GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
    GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
    GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
    - GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
    + GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
    GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
    GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
    GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
    @@ -478,12 +482,12 @@ static struct mtk_composite infra_muxes[] = {

    static struct mtk_composite top_muxes[] = {
    /* CLK_CFG_0 */
    - MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
    - 0x040, 0, 3, 7),
    - MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
    - 0x040, 8, 1, 15),
    - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
    - 0x040, 16, 1, 23),
    + MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
    + 0x040, 0, 3, 7, CLK_IS_CRITICAL),
    + MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
    + 0x040, 8, 1, 15, CLK_IS_CRITICAL),
    + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
    + 0x040, 16, 1, 23, CLK_IS_CRITICAL),
    MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
    0x040, 24, 3, 31),

    @@ -621,10 +625,6 @@ static int mtk_topckgen_init(struct platform_device *pdev)
    mtk_clk_register_gates(&pdev->dev, node, top_clks,
    ARRAY_SIZE(top_clks), clk_data);

    - clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
    - clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
    - clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
    -
    return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
    }

    @@ -667,9 +667,6 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
    mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
    ARRAY_SIZE(apmixed_clks), clk_data);

    - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
    - clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
    -
    return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
    }

    @@ -697,8 +694,6 @@ static int mtk_pericfg_init(struct platform_device *pdev)
    if (r)
    return r;

    - clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
    -
    mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);

    return 0;
    --
    2.39.1
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